Abstract
This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.
| Original language | English |
|---|---|
| Title of host publication | 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 938-941 |
| Number of pages | 4 |
| Volume | Part F134147 |
| ISBN (Electronic) | 9781538606407 |
| DOIs | |
| Publication status | Published - 2018 Jan 8 |
| Event | 2017 IEEE Asia Pacific Microwave Conference, APMC 2017 - Kuala Lumpur, Malaysia Duration: 2017 Nov 13 → 2017 Nov 16 |
Other
| Other | 2017 IEEE Asia Pacific Microwave Conference, APMC 2017 |
|---|---|
| Country | Malaysia |
| City | Kuala Lumpur |
| Period | 17/11/13 → 17/11/16 |
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Keywords
- 56-nm SOI CMOS
- Feedback Loop
- LC bias circuit
- LC-VCO IC
- Low-power
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
18-GHz band low-power LC VCO IC using LC bias circuit in 56-nm SOI CMOS. / Xu, Xiao; Chen, Cuilin; Sugiura, Tsuyoshi; Yoshimasu, Toshihiko.
2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings. Vol. Part F134147 Institute of Electrical and Electronics Engineers Inc., 2018. p. 938-941.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 18-GHz band low-power LC VCO IC using LC bias circuit in 56-nm SOI CMOS
AU - Xu, Xiao
AU - Chen, Cuilin
AU - Sugiura, Tsuyoshi
AU - Yoshimasu, Toshihiko
PY - 2018/1/8
Y1 - 2018/1/8
N2 - This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.
AB - This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.
KW - 56-nm SOI CMOS
KW - Feedback Loop
KW - LC bias circuit
KW - LC-VCO IC
KW - Low-power
UR - http://www.scopus.com/inward/record.url?scp=85044777763&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85044777763&partnerID=8YFLogxK
U2 - 10.1109/APMC.2017.8251604
DO - 10.1109/APMC.2017.8251604
M3 - Conference contribution
AN - SCOPUS:85044777763
VL - Part F134147
SP - 938
EP - 941
BT - 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -