18-GHz band low-power LC VCO IC using LC bias circuit in 56-nm SOI CMOS

Xiao Xu; Cuilin Chen; Tsuyoshi Sugiura; Toshihiko Yoshimasu

doi:10.1109/APMC.2017.8251604

18-GHz band low-power LC VCO IC using LC bias circuit in 56-nm SOI CMOS

Xiao Xu, Cuilin Chen, Tsuyoshi Sugiura, Toshihiko Yoshimasu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.

Original language	English
Title of host publication	2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	938-941
Number of pages	4
Volume	Part F134147
ISBN (Electronic)	9781538606407
DOIs	https://doi.org/10.1109/APMC.2017.8251604
Publication status	Published - 2018 Jan 8
Event	2017 IEEE Asia Pacific Microwave Conference, APMC 2017 - Kuala Lumpur, Malaysia Duration: 2017 Nov 13 → 2017 Nov 16

Other

Other	2017 IEEE Asia Pacific Microwave Conference, APMC 2017
Country	Malaysia
City	Kuala Lumpur
Period	17/11/13 → 17/11/16

Keywords

56-nm SOI CMOS
Feedback Loop
LC bias circuit
LC-VCO IC
Low-power

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

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18-GHz band low-power LC VCO IC using LC bias circuit in 56-nm SOI CMOS. / Xu, Xiao; Chen, Cuilin; Sugiura, Tsuyoshi; Yoshimasu, Toshihiko.

2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings. Vol. Part F134147 Institute of Electrical and Electronics Engineers Inc., 2018. p. 938-941.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Xu, X, Chen, C, Sugiura, T & Yoshimasu, T 2018, 18-GHz band low-power LC VCO IC using LC bias circuit in 56-nm SOI CMOS. in 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings. vol. Part F134147, Institute of Electrical and Electronics Engineers Inc., pp. 938-941, 2017 IEEE Asia Pacific Microwave Conference, APMC 2017, Kuala Lumpur, Malaysia, 17/11/13. https://doi.org/10.1109/APMC.2017.8251604

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abstract = "This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.",

keywords = "56-nm SOI CMOS, Feedback Loop, LC bias circuit, LC-VCO IC, Low-power",

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N2 - This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.

AB - This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.

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