1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

Takashi Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Citations (Scopus)

Abstract

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under V dd=1V. The 1Mb chip with 2.19μm 2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Circuits, VLSIC 2012
Pages46-47
Number of pages2
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
Duration: 2012 Jun 132012 Jun 15

Other

Other2012 Symposium on VLSI Circuits, VLSIC 2012
CountryUnited States
CityHonolulu, HI
Period12/6/1312/6/15

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Random access storage
Data storage equipment
Static random access storage
Macros

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Ohsawa, T., Koike, H., Miura, S., Honjo, H., Tokutome, K., Ikeda, S., ... Endoh, T. (2012). 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. In 2012 Symposium on VLSI Circuits, VLSIC 2012 (pp. 46-47). [6243782] https://doi.org/10.1109/VLSIC.2012.6243782

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. / Ohsawa, Takashi; Koike, H.; Miura, S.; Honjo, H.; Tokutome, K.; Ikeda, S.; Hanyu, T.; Ohno, H.; Endoh, T.

2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 46-47 6243782.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ohsawa, T, Koike, H, Miura, S, Honjo, H, Tokutome, K, Ikeda, S, Hanyu, T, Ohno, H & Endoh, T 2012, 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. in 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243782, pp. 46-47, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 12/6/13. https://doi.org/10.1109/VLSIC.2012.6243782
Ohsawa T, Koike H, Miura S, Honjo H, Tokutome K, Ikeda S et al. 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. In 2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 46-47. 6243782 https://doi.org/10.1109/VLSIC.2012.6243782
Ohsawa, Takashi ; Koike, H. ; Miura, S. ; Honjo, H. ; Tokutome, K. ; Ikeda, S. ; Hanyu, T. ; Ohno, H. ; Endoh, T. / 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. 2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. pp. 46-47
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