2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

We introduce a 288-310 GHz frequency multiplier fabricated with 40 nm CMOS technology. With 410.3 mW power consumption, this frequency multiplier has a conversion gain of 4.52 dB including that of its driver amplifier. The proposed system for input power/phase control of the power combiner enhances the output power of the frequency multiplier to 2.37 dBm at 300 GHz.

Original languageEnglish
Title of host publication2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages28-30
Number of pages3
ISBN (Electronic)9781509040360
DOIs
Publication statusPublished - 2017 Sep 20
Externally publishedYes
Event2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017 - Seoul, Korea, Republic of
Duration: 2017 Aug 302017 Sep 1

Other

Other2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017
CountryKorea, Republic of
CitySeoul
Period17/8/3017/9/1

Keywords

  • Bias optimization
  • Phase mismatch
  • Power combiner
  • Quad-ratrace

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Instrumentation

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  • Cite this

    Katayama, K., Takano, K., Amakawa, S., Yoshida, T., & Fujishima, M. (2017). 2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS. In 2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017 (pp. 28-30). [8048279] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2017.8048279