2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS

Kosuke Katayama; Kyoya Takano; Shuhei Amakawa; Takeshi Yoshida; Minoru Fujishima

doi:10.1109/RFIT.2017.8048279

2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

We introduce a 288-310 GHz frequency multiplier fabricated with 40 nm CMOS technology. With 410.3 mW power consumption, this frequency multiplier has a conversion gain of 4.52 dB including that of its driver amplifier. The proposed system for input power/phase control of the power combiner enhances the output power of the frequency multiplier to 2.37 dBm at 300 GHz.

Original language	English
Title of host publication	2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	28-30
Number of pages	3
ISBN (Electronic)	9781509040360
DOIs	https://doi.org/10.1109/RFIT.2017.8048279
Publication status	Published - 2017 Sep 20
Externally published	Yes
Event	2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017 - Seoul, Korea, Republic of Duration: 2017 Aug 30 → 2017 Sep 1

Other

Other	2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017
Country	Korea, Republic of
City	Seoul
Period	17/8/30 → 17/9/1

Keywords

Bias optimization
Phase mismatch
Power combiner
Quad-ratrace

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Instrumentation

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2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS. / Katayama, Kosuke; Takano, Kyoya; Amakawa, Shuhei; Yoshida, Takeshi; Fujishima, Minoru.

2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 28-30 8048279.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Katayama, K, Takano, K, Amakawa, S, Yoshida, T & Fujishima, M 2017, 2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS. in 2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017., 8048279, Institute of Electrical and Electronics Engineers Inc., pp. 28-30, 2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017, Seoul, Korea, Republic of, 17/8/30. https://doi.org/10.1109/RFIT.2017.8048279

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abstract = "We introduce a 288-310 GHz frequency multiplier fabricated with 40 nm CMOS technology. With 410.3 mW power consumption, this frequency multiplier has a conversion gain of 4.52 dB including that of its driver amplifier. The proposed system for input power/phase control of the power combiner enhances the output power of the frequency multiplier to 2.37 dBm at 300 GHz.",

keywords = "Bias optimization, Phase mismatch, Power combiner, Quad-ratrace",

author = "Kosuke Katayama and Kyoya Takano and Shuhei Amakawa and Takeshi Yoshida and Minoru Fujishima",

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AU - Takano, Kyoya

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AU - Yoshida, Takeshi

AU - Fujishima, Minoru

PY - 2017/9/20

Y1 - 2017/9/20

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AB - We introduce a 288-310 GHz frequency multiplier fabricated with 40 nm CMOS technology. With 410.3 mW power consumption, this frequency multiplier has a conversion gain of 4.52 dB including that of its driver amplifier. The proposed system for input power/phase control of the power combiner enhances the output power of the frequency multiplier to 2.37 dBm at 300 GHz.

KW - Bias optimization

KW - Phase mismatch

KW - Power combiner

KW - Quad-ratrace

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2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS

Abstract

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Keywords

ASJC Scopus subject areas

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