24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits

Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A post-fabrication dual supply voltage (V DD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (V DDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average V DD below V DDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC'S circuit fabricated in 65nm CMOS. The layout of DES CODEC'S is divided into 64 V DD domains and each domain size is 54μm x 63.2μm. High V DD (V DDH) or low V DD (V DDL) is applied to each domain and the selection of V DD's is performed based on multiple built-in self tests. V DDH is selected in V DDmin-critical domains, while V DDL is selected in V DDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, V DDH =437mV, and V DDL =397mV.

Original languageEnglish
Title of host publicationProceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012
Pages586-591
Number of pages6
DOIs
Publication statusPublished - 2012 Jul 16
Event13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA, United States
Duration: 2012 Mar 192012 Mar 21

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other13th International Symposium on Quality Electronic Design, ISQED 2012
CountryUnited States
CitySanta Clara, CA
Period12/3/1912/3/21

Keywords

  • Low voltage logic circuit
  • dual supply voltage
  • fine-grain power supply voltage
  • low power

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Yasufuku, T., Hirairi, K., Pu, Y., Zheng, Y. F., Takahashi, R., Sasaki, M., Fuketa, H., Muramatsu, A., Nomura, M., Shinohara, H., Takamiya, M., & Sakurai, T. (2012). 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits. In Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012 (pp. 586-591). [6187553] (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2012.6187553