25-ns 256K ×1/64K × 4 CMOS SRAM's

Shinpei Kayano, Katsuki Ichinose, Yoshio Kohno, Hirofumi Shinohara, Kenji Anami, Shuji Murakami, Tomohisa Wada, Yuji Kawai, Yoichi Akasaka

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Abstract

This paper describes 25-ns 256K CMOS static RAM's (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2.

Original languageEnglish
Pages (from-to)686-691
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume21
Issue number5
DOIs
Publication statusPublished - 1986
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kayano, S., Ichinose, K., Kohno, Y., Shinohara, H., Anami, K., Murakami, S., Wada, T., Kawai, Y., & Akasaka, Y. (1986). 25-ns 256K ×1/64K × 4 CMOS SRAM's. IEEE Journal of Solid-State Circuits, 21(5), 686-691. https://doi.org/10.1109/JSSC.1986.1052596