32-parallel SAD tree hardwired engine for variable block size motion estimation in HDTV1080p real-time encoding application

Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Ngfeng Li, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

H.264/AVC coding standard incorporates variable block size (VBS) motion estimation (ME) to improve the compression efficiency. For HDTV-1080p application, the massive computation and huge memory bandwidth by the large video frame size and the wide search range are two critical impediments to the real-time hardwired VB-SME engine design. In this paper, we present six techniques to circumvent these difficulties. First, the inter modes bellow 8 × 8 are eliminated in our design to reduce the hardware cost. Second, the low-pass filter based 4:1 down-sampling algorithm successfully reduces about 75% arithmetic computation in each search position. Third, the coarse to fine search scheme is made use of to reduce 25%-50% search candidates. Fourth, C+ memory organization is adopted to reduce the external IO bandwidth. Fifth, horizontal zigzag scan mode optimizes the search window memories. Finally, in circuit design, 4:2 compressor based CSA tree, multi-cycle path delay and 2 pipeline stage SAD tree techniques are utilized to improve the speed and reduce the hardware of each SAD tree. The hardwired integer motion estimation (IME) engine with 192 ×128 search range for HDTV1080p@30Hz is demonstrated in this paper. With TSMC 0.18μm 1P6M CMOS technology, it is implemented with 485.7k gates standard cells and 327.68k bit on chip memories. The power dissipation is 729mw at 200MHz clock speed.

Original languageEnglish
Title of host publication2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
Pages675-680
Number of pages6
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 - Shanghai, China
Duration: 2007 Oct 172007 Oct 19

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Conference

Conference2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
CountryChina
CityShanghai
Period07/10/1707/10/19

Keywords

  • H.264/AVC
  • HDTV1080p
  • Integer motion estimation
  • VLSI
  • Variable block size

ASJC Scopus subject areas

  • Media Technology
  • Signal Processing

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    Liu, Z., Song, Y., Shao, M., Li, S., Li, N., Goto, S., & Ikenaga, T. (2007). 32-parallel SAD tree hardwired engine for variable block size motion estimation in HDTV1080p real-time encoding application. In 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings (pp. 675-680). [4387630] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). https://doi.org/10.1109/SIPS.2007.4387630