3.3 V-only 16 Mb DINOR flash memory

Shin ichi Kobayashi*, Masaaki Mihara, Yoshikazu Miyawaki, Motoharu Ishii, Tomoshi Futatsuya, Akira Hosogane, Atsushi Ohba, Yasushi Terada, Natsuo Ajika, Yuichi Kunori, Kojiro Yuzuriha, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara, Yuji Uji

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Citations (Scopus)

Abstract

A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm 2. 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherIEEE
Volume38
Publication statusPublished - 1995 Feb
Externally publishedYes
EventProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1995 Feb 151995 Feb 17

Other

OtherProceedings of the 1995 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period95/2/1595/2/17

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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