34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON.

Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, Shimpei Kayano

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

A 128-kb word multiplied by 8-b CMOS SRAM with an access time of 34 ns and a standby current of 2 mu A is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0. 8 mu m minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transition detection (ATD) are used. This RAM has a flash-clear function in which logical zeros are written into all memory cells in less than 1 mu s.

Original languageEnglish
Pages (from-to)727-732
Number of pages6
JournalIEEE Journal of Solid-State Circuits
VolumeSC-22
Issue number5
Publication statusPublished - 1987 Oct
Externally publishedYes

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Static random access storage
Random access storage
Polysilicon
Aluminum
Data storage equipment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Wada, T., Hirose, T., Shinohara, H., Kawai, Y., Yuzuriha, K., Kohno, Y., & Kayano, S. (1987). 34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON. IEEE Journal of Solid-State Circuits, SC-22(5), 727-732.

34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON. / Wada, Tomohisa; Hirose, Toshihiko; Shinohara, Hirofumi; Kawai, Yuji; Yuzuriha, Kojiro; Kohno, Yoshio; Kayano, Shimpei.

In: IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, 10.1987, p. 727-732.

Research output: Contribution to journalArticle

Wada, T, Hirose, T, Shinohara, H, Kawai, Y, Yuzuriha, K, Kohno, Y & Kayano, S 1987, '34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON.', IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, pp. 727-732.
Wada T, Hirose T, Shinohara H, Kawai Y, Yuzuriha K, Kohno Y et al. 34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON. IEEE Journal of Solid-State Circuits. 1987 Oct;SC-22(5):727-732.
Wada, Tomohisa ; Hirose, Toshihiko ; Shinohara, Hirofumi ; Kawai, Yuji ; Yuzuriha, Kojiro ; Kohno, Yoshio ; Kayano, Shimpei. / 34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON. In: IEEE Journal of Solid-State Circuits. 1987 ; Vol. SC-22, No. 5. pp. 727-732.
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