34ns 256Mb DRAM with boosted sense-ground scheme

Mikio Asakura, Tsukasa Ohishi, Masaki Tsukude, Shigeki Tomishima, Hideto Hidaka, Kazutami Anmoto, Kazuyasu Fujishima, Takahisa Eimori, Yoshikazu Ohno, Tadashi Nishimura, Masatoshi Yasunaga, Takashi Kondon, Shin ichi Satoh, Tsutomu Yoshihara, Kiyoshi Demizu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)


This paper describes boosted sense-ground (BSG) scheme extends the data retention time of a 256Mb DRAM. This scheme features a `L' bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs). A chip-scale package (CSP) technique is used to reduce package size to near chip size. A perspective view of the package is shown. The experimental 256Mb DRAM uses 0.25μm CMOS technology with triple-level metal. cs is 25fF with a 0. 72μm2 cell. The chip is 304mm2. The power supply is regulated internally to 2.5V.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Number of pages2
ISBN (Print)0780318455
Publication statusPublished - 1994
Externally publishedYes
EventProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1994 Feb 161994 Feb 18


OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Engineering(all)


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