35 NS 16K NMOS STATIC RAM.

Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Yoshihiro Hirata, Hiroshi Harada, Takao Nakano

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

An NMOS 16K multiplied by 1 bit fully static MOS RAM with 35 ns access time has been developed. High speed access time was achieved by the combination of an NMOS process with the 2. 2 mu m gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mw and 22. 5 mw, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.

Original languageEnglish
Pages (from-to)815-820
Number of pages6
JournalIEEE Journal of Solid-State Circuits
VolumeSC-17
Issue number5
Publication statusPublished - 1982 Oct
Externally publishedYes

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Random access storage
Alpha particles
Time delay
Energy dissipation
Transistors
Electrons
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Anami, K., Yoshimoto, M., Shinohara, H., Hirata, Y., Harada, H., & Nakano, T. (1982). 35 NS 16K NMOS STATIC RAM. IEEE Journal of Solid-State Circuits, SC-17(5), 815-820.

35 NS 16K NMOS STATIC RAM. / Anami, Kenji; Yoshimoto, Masahiko; Shinohara, Hirofumi; Hirata, Yoshihiro; Harada, Hiroshi; Nakano, Takao.

In: IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, 10.1982, p. 815-820.

Research output: Contribution to journalArticle

Anami, K, Yoshimoto, M, Shinohara, H, Hirata, Y, Harada, H & Nakano, T 1982, '35 NS 16K NMOS STATIC RAM.', IEEE Journal of Solid-State Circuits, vol. SC-17, no. 5, pp. 815-820.
Anami K, Yoshimoto M, Shinohara H, Hirata Y, Harada H, Nakano T. 35 NS 16K NMOS STATIC RAM. IEEE Journal of Solid-State Circuits. 1982 Oct;SC-17(5):815-820.
Anami, Kenji ; Yoshimoto, Masahiko ; Shinohara, Hirofumi ; Hirata, Yoshihiro ; Harada, Hiroshi ; Nakano, Takao. / 35 NS 16K NMOS STATIC RAM. In: IEEE Journal of Solid-State Circuits. 1982 ; Vol. SC-17, No. 5. pp. 815-820.
@article{bb3a7a338cac47949f7c6d9db563ad35,
title = "35 NS 16K NMOS STATIC RAM.",
abstract = "An NMOS 16K multiplied by 1 bit fully static MOS RAM with 35 ns access time has been developed. High speed access time was achieved by the combination of an NMOS process with the 2. 2 mu m gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mw and 22. 5 mw, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.",
author = "Kenji Anami and Masahiko Yoshimoto and Hirofumi Shinohara and Yoshihiro Hirata and Hiroshi Harada and Takao Nakano",
year = "1982",
month = "10",
language = "English",
volume = "SC-17",
pages = "815--820",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - 35 NS 16K NMOS STATIC RAM.

AU - Anami, Kenji

AU - Yoshimoto, Masahiko

AU - Shinohara, Hirofumi

AU - Hirata, Yoshihiro

AU - Harada, Hiroshi

AU - Nakano, Takao

PY - 1982/10

Y1 - 1982/10

N2 - An NMOS 16K multiplied by 1 bit fully static MOS RAM with 35 ns access time has been developed. High speed access time was achieved by the combination of an NMOS process with the 2. 2 mu m gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mw and 22. 5 mw, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.

AB - An NMOS 16K multiplied by 1 bit fully static MOS RAM with 35 ns access time has been developed. High speed access time was achieved by the combination of an NMOS process with the 2. 2 mu m gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mw and 22. 5 mw, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.

UR - http://www.scopus.com/inward/record.url?scp=0020193696&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0020193696&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0020193696

VL - SC-17

SP - 815

EP - 820

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -