39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

Yasue Yamamoto, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

Research output: Contribution to journalArticle

Abstract

We propose novel circuit techniques for 1 clock (1CLK) 1 read/1 write (1R/1W) 2-port static random-access memories (SRAMs) to improve read access time (tAC) and write margins at low voltages. Two-stage read boost (TSR-BST) and write word line boost (WWL-BST) after the read sensing schemes have been proposed. TSR-BST reduces the worst read bit line (RBL) delay by 61% and RBL amplitude by 10% at VDD = 0.5 V, which improves tAC by 39% and reduces energy dissipation by 11% at VDD = 0.55V. WWL-BST after read sensing scheme improves minimum operating voltage (Vmin) by 140mV. A 32 kbit 1CLK 1R/1W 2-port SRAM with TSR-BSTand WWL-BST has been developed using a 40 nm CMOS.

Original languageEnglish
Article number04EF13
JournalJapanese Journal of Applied Physics
Volume55
Issue number4
DOIs
Publication statusPublished - 2016 Apr 1

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access time
random access memory
acceleration (physics)
Clocks
Data storage equipment
Electric delay lines
Electric potential
Energy dissipation
clocks
energy
Networks (circuits)
delay lines
low voltage
margins
CMOS
energy dissipation
electric potential

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme. / Yamamoto, Yasue; Moriwaki, Shinichi; Kawasumi, Atsushi; Miyano, Shinji; Shinohara, Hirofumi.

In: Japanese Journal of Applied Physics, Vol. 55, No. 4, 04EF13, 01.04.2016.

Research output: Contribution to journalArticle

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