4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomehisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsLewis Winner, Jack A.A. Raper, M. Winner, J. Raper, R.G. Swartz
PublisherLewis Winner
Pages62-63
Number of pages2
Publication statusPublished - 1985
Externally publishedYes

Fingerprint

Static random access storage
Random access storage
MOSFET devices
Polysilicon
Aluminum
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., ... Kayano, S. (1985). 4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE. In L. Winner, J. A. A. Raper, M. Winner, J. Raper, & R. G. Swartz (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 62-63). Lewis Winner.

4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE. / Shinohara, Hirofumi; Anami, Kenji; Ichinose, Katsuki; Wada, Tomehisa; Kohno, Yoshio; Kawai, Yuji; Akasaka, Yoichi; Kayano, Shinpei.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Lewis Winner; Jack A.A. Raper; M. Winner; J. Raper; R.G. Swartz. Lewis Winner, 1985. p. 62-63.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shinohara, H, Anami, K, Ichinose, K, Wada, T, Kohno, Y, Kawai, Y, Akasaka, Y & Kayano, S 1985, 4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE. in L Winner, JAA Raper, M Winner, J Raper & RG Swartz (eds), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Lewis Winner, pp. 62-63.
Shinohara H, Anami K, Ichinose K, Wada T, Kohno Y, Kawai Y et al. 4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE. In Winner L, Raper JAA, Winner M, Raper J, Swartz RG, editors, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Lewis Winner. 1985. p. 62-63
Shinohara, Hirofumi ; Anami, Kenji ; Ichinose, Katsuki ; Wada, Tomehisa ; Kohno, Yoshio ; Kawai, Yuji ; Akasaka, Yoichi ; Kayano, Shinpei. / 4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / Lewis Winner ; Jack A.A. Raper ; M. Winner ; J. Raper ; R.G. Swartz. Lewis Winner, 1985. pp. 62-63
@inproceedings{eac01f0778874da399c34df2e0844f98,
title = "4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.",
abstract = "Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.",
author = "Hirofumi Shinohara and Kenji Anami and Katsuki Ichinose and Tomehisa Wada and Yoshio Kohno and Yuji Kawai and Yoichi Akasaka and Shinpei Kayano",
year = "1985",
language = "English",
pages = "62--63",
editor = "Lewis Winner and Raper, {Jack A.A.} and M. Winner and J. Raper and R.G. Swartz",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Lewis Winner",

}

TY - GEN

T1 - 4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

AU - Shinohara, Hirofumi

AU - Anami, Kenji

AU - Ichinose, Katsuki

AU - Wada, Tomehisa

AU - Kohno, Yoshio

AU - Kawai, Yuji

AU - Akasaka, Yoichi

AU - Kayano, Shinpei

PY - 1985

Y1 - 1985

N2 - Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

AB - Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

UR - http://www.scopus.com/inward/record.url?scp=0022207549&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022207549&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0022207549

SP - 62

EP - 63

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Winner, Lewis

A2 - Raper, Jack A.A.

A2 - Winner, M.

A2 - Raper, J.

A2 - Swartz, R.G.

PB - Lewis Winner

ER -