4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomehisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano

Research output: Contribution to journalConference articlepeer-review

7 Citations (Scopus)

Abstract

Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

Original languageEnglish
Pages (from-to)62-63
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 1985 Dec 1
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.'. Together they form a unique fingerprint.

Cite this