Abstract
A 5-V 4-Mb word multiplied by 1-b/1-Mb word multiplied by 4-b dynamic RAM with a static column mode and fast page mode has been built in a 0. 8 mu m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10. 9 mu m**2 and requires only a 2 mu m trench to obtain a storage capacitor of 50 fF with 10 nm SiO//2 equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C//B-to-C//S capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300 mil dual-in-line package with performances of 90 ns RAS access time and 30 ns column address access time.
Original language | English |
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Pages (from-to) | 643-650 |
Number of pages | 8 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | SC-22 |
Issue number | 5 |
Publication status | Published - 1987 Oct |
Externally published | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering