Abstract
A 32K words by 8-bit static RAM fabricated with a CMOS technology. is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1. 3- mu m design rule allowed layout of the NMOS memory cell in an area of 116. 0 mu m**2 and the die in 49. 6 mm**2.
| Original language | English |
|---|---|
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | SC-20 |
| Issue number | 5 |
| Publication status | Published - 1985 Oct |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE. / Shinohara, Hirofumi; Anami, Kenji; Ichinose, Katsuki; Wada, Tomohisa; Kohno, Yoshio; Kawai, Yuji; Akasaka, Yoichi; Kayano, Shinpei.
In: IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 5, 10.1985.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - 45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE.
AU - Shinohara, Hirofumi
AU - Anami, Kenji
AU - Ichinose, Katsuki
AU - Wada, Tomohisa
AU - Kohno, Yoshio
AU - Kawai, Yuji
AU - Akasaka, Yoichi
AU - Kayano, Shinpei
PY - 1985/10
Y1 - 1985/10
N2 - A 32K words by 8-bit static RAM fabricated with a CMOS technology. is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1. 3- mu m design rule allowed layout of the NMOS memory cell in an area of 116. 0 mu m**2 and the die in 49. 6 mm**2.
AB - A 32K words by 8-bit static RAM fabricated with a CMOS technology. is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1. 3- mu m design rule allowed layout of the NMOS memory cell in an area of 116. 0 mu m**2 and the die in 49. 6 mm**2.
UR - http://www.scopus.com/inward/record.url?scp=0022138789&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0022138789&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0022138789
VL - SC-20
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 5
ER -