46% Peak PAE 28 GHz High Linearity Stacked-FET Power Amplifier IC with a Novel Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS

Tsuyoshi Sugiura, Toshihiko Yoshimasu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 28 GHz high linearity power amplifier (PA) IC with a novel two-step adaptively controlled bias circuit for 5th generation (5G) mobile terminal applications in a 45-nm silicon on insulator (SOI) CMOS process. The novel bias circuit adaptively controls the gate voltage of a stacked-FET by a step procedure to improve the 1dB compression point (P1dB) and efficiency in the several-dB back-off region. The PA employs a 3-stacked-FET structure to overcome the low breakdown voltage issue in scaled MOSFETs. At a supply voltage of 3.5 V, the fabricated PA exhibits a peak power added efficiency (PAE) of 46.0%, a saturated output power of 20.5 dBm, a 3 dB output power back-off efficiency of 35.2%, a 6 dB output power back-off efficiency of 26.0% and a small signal gain of 15.0 dB. The PA IC occupies only 0.23 mm2.

Original languageEnglish
Title of host publication2022 17th European Microwave Integrated Circuits Conference, EuMIC 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages165-168
Number of pages4
ISBN (Electronic)9782874870705
DOIs
Publication statusPublished - 2022
Event17th European Microwave Integrated Circuits Conference, EuMIC 2022 - Milan, Italy
Duration: 2022 Sep 262022 Sep 27

Publication series

Name2022 17th European Microwave Integrated Circuits Conference, EuMIC 2022

Conference

Conference17th European Microwave Integrated Circuits Conference, EuMIC 2022
Country/TerritoryItaly
CityMilan
Period22/9/2622/9/27

Keywords

  • adaptive bias
  • high back-off efficiency
  • high linearity SOI CMOS
  • stacked-FET

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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