5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

S. Kimura, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, M. Aoki, T. Kisu, H. Sunami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.

Original languageEnglish
Title of host publicationConference on Solid State Devices and Materials
PublisherJapan Soc of Applied Physics
Pages19-22
Number of pages4
ISBN (Print)4930813212
Publication statusPublished - 1987

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kimura, S., Kawamoto, Y., Hasegawa, N., Hiraiwa, A., Horiguchi, M., Aoki, M., Kisu, T., & Sunami, H. (1987). 5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY. In Conference on Solid State Devices and Materials (pp. 19-22). Japan Soc of Applied Physics.