5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

S. Kimura; Y. Kawamoto; N. Hasegawa; A. Hiraiwa; M. Horiguchi; M. Aoki; T. Kisu; H. Sunami

5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

S. Kimura^*, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, M. Aoki, T. Kisu, H. Sunami

^*Corresponding author for this work

Research Organization for Nano & Life Innovation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.

Original language	English
Title of host publication	Conference on Solid State Devices and Materials
Publisher	Japan Soc of Applied Physics
Pages	19-22
Number of pages	4
ISBN (Print)	4930813212
Publication status	Published - 1987

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.",

abstract = "A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.",

author = "S. Kimura and Y. Kawamoto and N. Hasegawa and A. Hiraiwa and M. Horiguchi and M. Aoki and T. Kisu and H. Sunami",

year = "1987",

language = "English",

isbn = "4930813212",

pages = "19--22",

booktitle = "Conference on Solid State Devices and Materials",

publisher = "Japan Soc of Applied Physics",

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T1 - 5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

AU - Kimura, S.

AU - Kawamoto, Y.

AU - Hasegawa, N.

AU - Hiraiwa, A.

AU - Horiguchi, M.

AU - Aoki, M.

AU - Kisu, T.

AU - Sunami, H.

PY - 1987

Y1 - 1987

N2 - A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.

AB - A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.

UR - http://www.scopus.com/inward/record.url?scp=0023594258&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023594258&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0023594258

SN - 4930813212

SP - 19

EP - 22

BT - Conference on Solid State Devices and Materials

PB - Japan Soc of Applied Physics

ER -

5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

Abstract

ASJC Scopus subject areas

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