5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

S. Kimura; Y. Kawamoto; N. Hasegawa; A. Hiraiwa; M. Horiguchi; M. Aoki; T. Kisu; H. Sunami

5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

S. Kimura, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, M. Aoki, T. Kisu, H. Sunami

Research Organization for Nano & Life Innovation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.

Original language	English
Title of host publication	Conference on Solid State Devices and Materials
Publisher	Japan Soc of Applied Physics
Pages	19-22
Number of pages	4
ISBN (Print)	4930813212
Publication status	Published - 1987

ASJC Scopus subject areas

Engineering(all)

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Kimura, S., Kawamoto, Y., Hasegawa, N., Hiraiwa, A., Horiguchi, M., Aoki, M., Kisu, T., & Sunami, H. (1987). 5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY. In Conference on Solid State Devices and Materials (pp. 19-22). Japan Soc of Applied Physics.

5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY. / Kimura, S.; Kawamoto, Y.; Hasegawa, N.; Hiraiwa, A.; Horiguchi, M.; Aoki, M.; Kisu, T.; Sunami, H.

Conference on Solid State Devices and Materials. Japan Soc of Applied Physics, 1987. p. 19-22.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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