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5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.
S. Kimura*, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, M. Aoki, T. Kisu, H. Sunami
*Corresponding author for this work
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
8
Citations
(Scopus)