5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

S. Kimura, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, M. Aoki, T. Kisu, H. Sunami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

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Engineering & Materials Science