5-V-only one-transistor 256K EEPROM with page-mode erase

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

Research output: Contribution to journalArticle

6 Citations (Scopus)


Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is five per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5-μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7 × 8 μm2 and the chip size is 5.55 × 7.05 mm2. The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC.

Original languageEnglish
Pages (from-to)911-915
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number4
Publication statusPublished - 1989 Aug
Externally publishedYes


ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Nakayama, T., Miyawaki, Y., Kobayashi, K., Terada, Y., Arima, H., Matsukawa, T., & Yoshihara, T. (1989). 5-V-only one-transistor 256K EEPROM with page-mode erase. IEEE Journal of Solid-State Circuits, 24(4), 911-915. https://doi.org/10.1109/4.34070