50 ns video signal processor

Shin ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu ichi Kato, Atsushi Maeda, Yasutaka Horiba, Hideo Ohira, Yoshi aki Katoh, Mamoru Iwatsuki, Kin ya Tabuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
PublisherPubl by IEEE
Pages168-169, 328
Volume32
Publication statusPublished - 1989
Externally publishedYes
EventIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
Duration: 1989 Feb 151989 Feb 17

Other

OtherIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
CityNew York, NY, USA
Period89/2/1589/2/17

Fingerprint

Digital signal processors
Data transfer
Video signal processing
Parallel architectures
Voice/data communication systems
Transistors
Pipelines
Communication
Metals

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Nakagawa, S. I., Terane, H., Matsumura, T., Segawa, H., Yoshimoto, M., Shinohara, H., ... Tabuchi, K. Y. (1989). 50 ns video signal processor. In Anon (Ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 32, pp. 168-169, 328). Publ by IEEE.

50 ns video signal processor. / Nakagawa, Shin ichi; Terane, Hideyuki; Matsumura, Tetsuya; Segawa, Hiroshi; Yoshimoto, Masahiko; Shinohara, Hirofumi; Kato, Shu ichi; Maeda, Atsushi; Horiba, Yasutaka; Ohira, Hideo; Katoh, Yoshi aki; Iwatsuki, Mamoru; Tabuchi, Kin ya.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Anon. Vol. 32 Publ by IEEE, 1989. p. 168-169, 328.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakagawa, SI, Terane, H, Matsumura, T, Segawa, H, Yoshimoto, M, Shinohara, H, Kato, SI, Maeda, A, Horiba, Y, Ohira, H, Katoh, YA, Iwatsuki, M & Tabuchi, KY 1989, 50 ns video signal processor. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 32, Publ by IEEE, pp. 168-169, 328, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989), New York, NY, USA, 89/2/15.
Nakagawa SI, Terane H, Matsumura T, Segawa H, Yoshimoto M, Shinohara H et al. 50 ns video signal processor. In Anon, editor, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 32. Publ by IEEE. 1989. p. 168-169, 328
Nakagawa, Shin ichi ; Terane, Hideyuki ; Matsumura, Tetsuya ; Segawa, Hiroshi ; Yoshimoto, Masahiko ; Shinohara, Hirofumi ; Kato, Shu ichi ; Maeda, Atsushi ; Horiba, Yasutaka ; Ohira, Hideo ; Katoh, Yoshi aki ; Iwatsuki, Mamoru ; Tabuchi, Kin ya. / 50 ns video signal processor. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / Anon. Vol. 32 Publ by IEEE, 1989. pp. 168-169, 328
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