50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.

Takao Kaneko, Hironori Yamauchi, Atsushi Iwata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.

Original languageEnglish
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
PublisherIEEE
Pages401-404
Number of pages4
Publication statusPublished - 1986
Externally publishedYes

Fingerprint

Digital signal processors
very large scale integration
floating
central processing units
ROM
arithmetic and logic units
high speed
Transistors
Pipelines
CMOS
transistors
chips
cycles

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Acoustics and Ultrasonics

Cite this

Kaneko, T., Yamauchi, H., & Iwata, A. (1986). 50NS FLOATING-POINT SIGNAL PROCESSOR VLSI. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (pp. 401-404). IEEE.

50NS FLOATING-POINT SIGNAL PROCESSOR VLSI. / Kaneko, Takao; Yamauchi, Hironori; Iwata, Atsushi.

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE, 1986. p. 401-404.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kaneko, T, Yamauchi, H & Iwata, A 1986, 50NS FLOATING-POINT SIGNAL PROCESSOR VLSI. in ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE, pp. 401-404.
Kaneko T, Yamauchi H, Iwata A. 50NS FLOATING-POINT SIGNAL PROCESSOR VLSI. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE. 1986. p. 401-404
Kaneko, Takao ; Yamauchi, Hironori ; Iwata, Atsushi. / 50NS FLOATING-POINT SIGNAL PROCESSOR VLSI. ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. IEEE, 1986. pp. 401-404
@inproceedings{fbca90746a3c4dde93725b0faee4a42b,
title = "50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.",
abstract = "A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.",
author = "Takao Kaneko and Hironori Yamauchi and Atsushi Iwata",
year = "1986",
language = "English",
pages = "401--404",
booktitle = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",
publisher = "IEEE",

}

TY - GEN

T1 - 50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.

AU - Kaneko, Takao

AU - Yamauchi, Hironori

AU - Iwata, Atsushi

PY - 1986

Y1 - 1986

N2 - A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.

AB - A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.

UR - http://www.scopus.com/inward/record.url?scp=0022908735&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022908735&partnerID=8YFLogxK

M3 - Conference contribution

SP - 401

EP - 404

BT - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

PB - IEEE

ER -