5V only 1 Tr. 256K EEPROM with page mode erase

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

Original languageEnglish
Title of host publication1988 Symp VLSI Circuits Dig Tech Pap
Editors Anon
Pages81-82
Number of pages2
Publication statusPublished - 1988
Externally publishedYes
Event1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan
Duration: 1988 Aug 221988 Aug 24

Other

Other1988 Symposium on VLSI Circuits - Digest of Technical Papers
CityTokyo, Japan
Period88/8/2288/8/24

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Nakayama, T., Miyawaki, Y., Kobayashi, K., Terada, Y., Arima, H., Matsukawa, T., & Yoshihara, T. (1988). 5V only 1 Tr. 256K EEPROM with page mode erase. In Anon (Ed.), 1988 Symp VLSI Circuits Dig Tech Pap (pp. 81-82)