60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

An auto selective boost (ASB) scheme for slow SRAM memory cells in random variations has been proposed. ASB shortens the cycle time and decreases the average BL amplitude, which reduces both dynamic and leakage energy dissipation. The cycle time of SRAM is reduced by 60% at 0.5V using the proposed ASB scheme. By combining the ASB with a BL amplitude limiter (BAL), the energy dissipation is reduced by 55%. A 32Kbit SRAM with the ASB and BAL schemes has been fabricated by 40nm CMOS technology.

Original languageEnglish
Title of host publication2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages317-320
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 14
Event38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France
Duration: 2012 Sep 172012 Sep 21

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Other

Other38th European Solid State Circuits Conference, ESSCIRC 2012
CountryFrance
CityBordeaux
Period12/9/1712/9/21

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yamamoto, Y., Kawasumi, A., Moriwaki, S., Suzuki, T., Miyano, S., & Shinohara, H. (2012). 60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. In 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012 (pp. 317-320). [6341318] (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2012.6341318