60 ns 3.3 V 16 Mb DRAM

Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Oishi, Masaki Tsukude, Wataru Wakamiya, Shin ichi Satoh, Michihiro Yamada, Tsutomu Yoshihara, Takao Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
PublisherPubl by IEEE
Pages244-245, 352
Volume32
Publication statusPublished - 1989
Externally publishedYes
EventIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
Duration: 1989 Feb 151989 Feb 17

Other

OtherIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
CityNew York, NY, USA
Period89/2/1589/2/17

Fingerprint

Random access storage

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Arimoto, K., Fujishima, K., Matsuda, Y., Oishi, T., Tsukude, M., Wakamiya, W., ... Nakano, T. (1989). 60 ns 3.3 V 16 Mb DRAM. In Anon (Ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 32, pp. 244-245, 352). Publ by IEEE.

60 ns 3.3 V 16 Mb DRAM. / Arimoto, Kazutami; Fujishima, Kazuyasu; Matsuda, Yoshio; Oishi, Tsukasa; Tsukude, Masaki; Wakamiya, Wataru; Satoh, Shin ichi; Yamada, Michihiro; Yoshihara, Tsutomu; Nakano, Takao.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Anon. Vol. 32 Publ by IEEE, 1989. p. 244-245, 352.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Arimoto, K, Fujishima, K, Matsuda, Y, Oishi, T, Tsukude, M, Wakamiya, W, Satoh, SI, Yamada, M, Yoshihara, T & Nakano, T 1989, 60 ns 3.3 V 16 Mb DRAM. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 32, Publ by IEEE, pp. 244-245, 352, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989), New York, NY, USA, 89/2/15.
Arimoto K, Fujishima K, Matsuda Y, Oishi T, Tsukude M, Wakamiya W et al. 60 ns 3.3 V 16 Mb DRAM. In Anon, editor, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 32. Publ by IEEE. 1989. p. 244-245, 352
Arimoto, Kazutami ; Fujishima, Kazuyasu ; Matsuda, Yoshio ; Oishi, Tsukasa ; Tsukude, Masaki ; Wakamiya, Wataru ; Satoh, Shin ichi ; Yamada, Michihiro ; Yoshihara, Tsutomu ; Nakano, Takao. / 60 ns 3.3 V 16 Mb DRAM. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / Anon. Vol. 32 Publ by IEEE, 1989. pp. 244-245, 352
@inproceedings{2d33fe56de0e4b74be815eb086797984,
title = "60 ns 3.3 V 16 Mb DRAM",
abstract = "The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.",
author = "Kazutami Arimoto and Kazuyasu Fujishima and Yoshio Matsuda and Tsukasa Oishi and Masaki Tsukude and Wataru Wakamiya and Satoh, {Shin ichi} and Michihiro Yamada and Tsutomu Yoshihara and Takao Nakano",
year = "1989",
language = "English",
volume = "32",
pages = "244--245, 352",
editor = "Anon",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - 60 ns 3.3 V 16 Mb DRAM

AU - Arimoto, Kazutami

AU - Fujishima, Kazuyasu

AU - Matsuda, Yoshio

AU - Oishi, Tsukasa

AU - Tsukude, Masaki

AU - Wakamiya, Wataru

AU - Satoh, Shin ichi

AU - Yamada, Michihiro

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

PY - 1989

Y1 - 1989

N2 - The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.

AB - The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.

UR - http://www.scopus.com/inward/record.url?scp=0024943742&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024943742&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024943742

VL - 32

SP - 244-245, 352

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Anon, null

PB - Publ by IEEE

ER -