60 ns access 32 kByte 3-transistor flash for low power embedded applications

Tamio Ikehashi, Junichiro Noda, Kenichi Imamiya, Masaaki Ichikawa, Akira Iwata, Takuya Futatsuyama

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

3-Transistor Flash (3-Tr) is a new flash memory suited for embedded application. The 32 kByte memory cell has the low power erase/program characteristic of NAND flash, and the size of the cell fabricated in a 0.4 um NAND flash technology is 4.36 μm2. This is about 1/8 of the EEPROM cells size with the same design rule. Two circuit technologies, a low power sensing scheme and a double stage boosting scheme, are proposed. The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during program mode.

Original languageEnglish
Pages162-165
Number of pages4
Publication statusPublished - 2000 Jan 1
Event2000 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 2000 Jun 152000 Jun 17

Conference

Conference2000 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period00/6/1500/6/17

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Ikehashi, T., Noda, J., Imamiya, K., Ichikawa, M., Iwata, A., & Futatsuyama, T. (2000). 60 ns access 32 kByte 3-transistor flash for low power embedded applications. 162-165. Paper presented at 2000 Symposium on VLSI Circuits, Honolulu, HI, USA, .