61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier

Toru Hisakado, Nobuyuki Kobayashi, Satoshi Goto, Takeshi Ikenaga, Kunihiko Higashi, Ichiro Kitao, Yukiyasu Tsunoo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

RSA, one of the public key cryptographies, is the most widely used for a wide variety of information systems. Especially, a compact, high-performance RSA LSI is highly desired for mobile applications, such as a smart card and a cellar phone. This paper describes a RSA Cryptography Co-processor LSI. It can process up to 2048-bit key data, which is requited to guarantee the high security level of RSA. Although a large computational complexity is required to process 2048-bit RSA, our proposed N bit-wise modular multiplier based on Montgomery multiplication algorithm enables to reduce 25% circuit amount compared with the conventional one. A chip capable of operating at 60 MHz was fabricated using 0.18 um TSMC CMOS technology. A total of 98.5 k gates (incl. SRAM and I/Q modules) have been integrated into a 2.2 × 2.2 mm chip. Evaluation result with IC test system shows that power dissipation is 61.5 mW when 20.48-bit RSA processing is operated at 40 MHz. This RSA LSI will make a significant contribution to the development of compact, high-performance secure information systems.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages63-66
Number of pages4
DOIs
Publication statusPublished - 2007
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu
Duration: 2007 Apr 262007 Apr 28

Other

Other2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CityHsinchu
Period07/4/2607/4/28

Fingerprint

Information systems
Smart cards
Static random access storage
Cryptography
Computational complexity
Energy dissipation
Coprocessor
Networks (circuits)
Processing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hisakado, T., Kobayashi, N., Goto, S., Ikenaga, T., Higashi, K., Kitao, I., & Tsunoo, Y. (2007). 61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 63-66). [4027496] https://doi.org/10.1109/VDAT.2006.258124

61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier. / Hisakado, Toru; Kobayashi, Nobuyuki; Goto, Satoshi; Ikenaga, Takeshi; Higashi, Kunihiko; Kitao, Ichiro; Tsunoo, Yukiyasu.

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 63-66 4027496.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hisakado, T, Kobayashi, N, Goto, S, Ikenaga, T, Higashi, K, Kitao, I & Tsunoo, Y 2007, 61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027496, pp. 63-66, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, 07/4/26. https://doi.org/10.1109/VDAT.2006.258124
Hisakado T, Kobayashi N, Goto S, Ikenaga T, Higashi K, Kitao I et al. 61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 63-66. 4027496 https://doi.org/10.1109/VDAT.2006.258124
Hisakado, Toru ; Kobayashi, Nobuyuki ; Goto, Satoshi ; Ikenaga, Takeshi ; Higashi, Kunihiko ; Kitao, Ichiro ; Tsunoo, Yukiyasu. / 61.5mW 2048-bit RSA cryptographic co-processor LSI based on N bit-wised modular multiplier. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. pp. 63-66
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