70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications

T. Matsumoto, S. Maeda, K. Ota, Y. Hirano, K. Eikyu, H. Sayama, T. Iwamatsu, K. Yamamoto, T. Katoh, Y. Yamaguchi, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, Masahide Inuishi

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21 Citations (Scopus)

Abstract

We achieved 135 GHz fmax and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of Vth variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

Original languageEnglish
Pages (from-to)219-222
Number of pages4
JournalUnknown Journal
Publication statusPublished - 2001
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Matsumoto, T., Maeda, S., Ota, K., Hirano, Y., Eikyu, K., Sayama, H., Iwamatsu, T., Yamamoto, K., Katoh, T., Yamaguchi, Y., Ipposhi, T., Oda, H., Maegawa, S., Inoue, Y., & Inuishi, M. (2001). 70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications. Unknown Journal, 219-222.