70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications

T. Matsumoto, S. Maeda, K. Ota, Y. Hirano, K. Eikyu, H. Sayama, T. Iwamatsu, K. Yamamoto*, T. Katoh, Y. Yamaguchi, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, M. Inuishi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

23 Citations (Scopus)

Abstract

We achieved 135 GHz fmax and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of Vth variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

Original languageEnglish
Pages (from-to)219-222
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2001 Dec 1
Externally publishedYes
EventIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
Duration: 2001 Dec 22001 Dec 5

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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