80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

H. Sayama, Y. Nishida, H. Oda, J. Tsuchimoto, H. Umeda, A. Teramoto, K. Eikyu, Y. Inoue, M. Inuishi

Research output: Contribution to journalConference articlepeer-review

11 Citations (Scopus)

Abstract

The fabrication of high drive current CMOSFET with 80 nanometer gate length was discussed. Short channel effects (SCE) and parasitic resistance in sub-0.1 micrometer CMOS were improved with the help of double offset-implanted sourse drain extension and silicon nitride deposition. A drive current of 830/400 micro ampere per nanometer with 2.5 nanometer gate insulator was achieved under 1 nanoampere per micrometer offstate leakage at 1.5V operation with 80 nanometer gate length.

Original languageEnglish
Pages (from-to)239-242
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2000 Dec 1
Externally publishedYes
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 2000 Dec 102000 Dec 13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Fingerprint Dive into the research topics of '80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process'. Together they form a unique fingerprint.

Cite this