80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

H. Sayama, Y. Nishida, H. Oda, J. Tsuchimoto, H. Umeda, A. Teramoto, K. Eikyu, Y. Inoue, Masahide Inuishi

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

The fabrication of high drive current CMOSFET with 80 nanometer gate length was discussed. Short channel effects (SCE) and parasitic resistance in sub-0.1 micrometer CMOS were improved with the help of double offset-implanted sourse drain extension and silicon nitride deposition. A drive current of 830/400 micro ampere per nanometer with 2.5 nanometer gate insulator was achieved under 1 nanoampere per micrometer offstate leakage at 1.5V operation with 80 nanometer gate length.

Original languageEnglish
Pages (from-to)239-242
Number of pages4
JournalUnknown Journal
Publication statusPublished - 2000
Externally publishedYes

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micrometers
Silicon nitride
silicon nitrides
Fabrication
Temperature
nitrides
temperature
CMOS
leakage
insulators
fabrication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sayama, H., Nishida, Y., Oda, H., Tsuchimoto, J., Umeda, H., Teramoto, A., ... Inuishi, M. (2000). 80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process. Unknown Journal, 239-242.

80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process. / Sayama, H.; Nishida, Y.; Oda, H.; Tsuchimoto, J.; Umeda, H.; Teramoto, A.; Eikyu, K.; Inoue, Y.; Inuishi, Masahide.

In: Unknown Journal, 2000, p. 239-242.

Research output: Contribution to journalArticle

Sayama, H, Nishida, Y, Oda, H, Tsuchimoto, J, Umeda, H, Teramoto, A, Eikyu, K, Inoue, Y & Inuishi, M 2000, '80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process', Unknown Journal, pp. 239-242.
Sayama H, Nishida Y, Oda H, Tsuchimoto J, Umeda H, Teramoto A et al. 80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process. Unknown Journal. 2000;239-242.
Sayama, H. ; Nishida, Y. ; Oda, H. ; Tsuchimoto, J. ; Umeda, H. ; Teramoto, A. ; Eikyu, K. ; Inoue, Y. ; Inuishi, Masahide. / 80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process. In: Unknown Journal. 2000 ; pp. 239-242.
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