8.8-ns 54×54-bit multiplier using new redundant binary architecture

Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Citations (Scopus)

Abstract

A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Editors Anon
PublisherPubl by IEEE
Pages202-205
Number of pages4
ISBN (Print)0818642300
Publication statusPublished - 1993
Externally publishedYes
EventProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
Duration: 1993 Oct 31993 Oct 6

Other

OtherProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityCambridge, MA, USA
Period93/10/393/10/6

Fingerprint

Networks (circuits)
Adders
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Makino, H., Nakase, Y., & Shinohara, H. (1993). 8.8-ns 54×54-bit multiplier using new redundant binary architecture. In Anon (Ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 202-205). Publ by IEEE.

8.8-ns 54×54-bit multiplier using new redundant binary architecture. / Makino, Hiroshi; Nakase, Yasunobu; Shinohara, Hirofumi.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. Publ by IEEE, 1993. p. 202-205.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Makino, H, Nakase, Y & Shinohara, H 1993, 8.8-ns 54×54-bit multiplier using new redundant binary architecture. in Anon (ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, pp. 202-205, Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Cambridge, MA, USA, 93/10/3.
Makino H, Nakase Y, Shinohara H. 8.8-ns 54×54-bit multiplier using new redundant binary architecture. In Anon, editor, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE. 1993. p. 202-205
Makino, Hiroshi ; Nakase, Yasunobu ; Shinohara, Hirofumi. / 8.8-ns 54×54-bit multiplier using new redundant binary architecture. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. editor / Anon. Publ by IEEE, 1993. pp. 202-205
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