TY - GEN
T1 - 8.8-ns 54×54-bit multiplier using new redundant binary architecture
AU - Makino, Hiroshi
AU - Nakase, Yasunobu
AU - Shinohara, Hirofumi
PY - 1993/12/1
Y1 - 1993/12/1
N2 - A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.
AB - A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.
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M3 - Conference contribution
AN - SCOPUS:0027866792
SN - 0818642300
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 202
EP - 205
BT - Proceedings - IEEE International Conference on Computer Design
A2 - Anon, null
PB - Publ by IEEE
T2 - Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Y2 - 3 October 1993 through 6 October 1993
ER -