Abstract
A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| Editors | Anon |
| Publisher | Publ by IEEE |
| Pages | 202-205 |
| Number of pages | 4 |
| ISBN (Print) | 0818642300 |
| Publication status | Published - 1993 |
| Externally published | Yes |
| Event | Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA Duration: 1993 Oct 3 → 1993 Oct 6 |
Other
| Other | Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 93/10/3 → 93/10/6 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
8.8-ns 54×54-bit multiplier using new redundant binary architecture. / Makino, Hiroshi; Nakase, Yasunobu; Shinohara, Hirofumi.
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. Publ by IEEE, 1993. p. 202-205.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 8.8-ns 54×54-bit multiplier using new redundant binary architecture
AU - Makino, Hiroshi
AU - Nakase, Yasunobu
AU - Shinohara, Hirofumi
PY - 1993
Y1 - 1993
N2 - A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.
AB - A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.
UR - http://www.scopus.com/inward/record.url?scp=0027866792&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0027866792&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027866792
SN - 0818642300
SP - 202
EP - 205
BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
A2 - Anon, null
PB - Publ by IEEE
ER -