8.8-ns 54×54-bit multiplier using new redundant binary architecture

Hiroshi Makino; Yasunobu Nakase; Hirofumi Shinohara

8.8-ns 54×54-bit multiplier using new redundant binary architecture

Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.

Original language	English
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors
Editors	Anon
Publisher	Publ by IEEE
Pages	202-205
Number of pages	4
ISBN (Print)	0818642300
Publication status	Published - 1993 Dec 1
Externally published	Yes
Event	Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA Duration: 1993 Oct 3 → 1993 Oct 6

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

Other	Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
City	Cambridge, MA, USA
Period	93/10/3 → 93/10/6

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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8.8-ns 54×54-bit multiplier using new redundant binary architecture. / Makino, Hiroshi; Nakase, Yasunobu; Shinohara, Hirofumi.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. Publ by IEEE, 1993. p. 202-205 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Makino, H, Nakase, Y & Shinohara, H 1993, 8.8-ns 54×54-bit multiplier using new redundant binary architecture. in Anon (ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Publ by IEEE, pp. 202-205, Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Cambridge, MA, USA, 93/10/3.

Makino, Hiroshi ; Nakase, Yasunobu ; Shinohara, Hirofumi. / 8.8-ns 54×54-bit multiplier using new redundant binary architecture. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. editor / Anon. Publ by IEEE, 1993. pp. 202-205 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

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abstract = "A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.",

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