90NS 1MB DRAM WITH MULTI-BIT TEST MODE.

Masaki Kumanoya, Kazuyasu Fujishima, Katsuhiro Tsukamoto, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

Summary form only given. A single 5-V, 1-Mb NMOS DRAM is described that uses reliable memory cells with a reduced electric field and a shared sensing scheme for a reasonable cell signal. A testability concept, a page-nibble function, including continuous nibble mode, and an effective redundancy circuit are included. The memory cell uses a half Vcc cell plate that reduces the electric field across the oxide of the memory capacity to 50% of that experienced with the conventional Vcc or Vss cell plate methods. A grounded epitaxial substrate is used to avoid the voltage bounce of the internally generated cell potential and minority carrier injection from the device inputs or peripheral circuits. The 35. 7- mu m**2 memory cell acts as a storage capacitance of 45 fF with 100-angstrom- thick oxide, while maintaining the electric field as low as 2 MV/cm.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsLewis Winner, Jack A.A. Raper, M. Winner, J. Raper, R.G. Swartz
PublisherLewis Winner
Pages240-241
Number of pages2
Publication statusPublished - 1985
Externally publishedYes

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kumanoya, M., Fujishima, K., Tsukamoto, K., Nishimura, Y., Saito, K., Matsukawa, T., Yoshihara, T., & Nakano, T. (1985). 90NS 1MB DRAM WITH MULTI-BIT TEST MODE. In L. Winner, J. A. A. Raper, M. Winner, J. Raper, & R. G. Swartz (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 240-241). Lewis Winner.