90NS 1MB DRAM WITH MULTI-BIT TEST MODE.

Masaki Kumanoya, Kazuyasu Fujishima, Katsuhiro Tsukamoto, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

Summary form only given. A single 5-V, 1-Mb NMOS DRAM is described that uses reliable memory cells with a reduced electric field and a shared sensing scheme for a reasonable cell signal. A testability concept, a page-nibble function, including continuous nibble mode, and an effective redundancy circuit are included. The memory cell uses a half Vcc cell plate that reduces the electric field across the oxide of the memory capacity to 50% of that experienced with the conventional Vcc or Vss cell plate methods. A grounded epitaxial substrate is used to avoid the voltage bounce of the internally generated cell potential and minority carrier injection from the device inputs or peripheral circuits. The 35. 7- mu m**2 memory cell acts as a storage capacitance of 45 fF with 100-angstrom- thick oxide, while maintaining the electric field as low as 2 MV/cm.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsLewis Winner, Jack A.A. Raper, M. Winner, J. Raper, R.G. Swartz
PublisherLewis Winner
Pages240-241
Number of pages2
Publication statusPublished - 1985
Externally publishedYes

Fingerprint

Dynamic random access storage
Data storage equipment
Electric fields
Oxides
Networks (circuits)
Redundancy
Capacitance
Electric potential
Substrates

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kumanoya, M., Fujishima, K., Tsukamoto, K., Nishimura, Y., Saito, K., Matsukawa, T., ... Nakano, T. (1985). 90NS 1MB DRAM WITH MULTI-BIT TEST MODE. In L. Winner, J. A. A. Raper, M. Winner, J. Raper, & R. G. Swartz (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 240-241). Lewis Winner.

90NS 1MB DRAM WITH MULTI-BIT TEST MODE. / Kumanoya, Masaki; Fujishima, Kazuyasu; Tsukamoto, Katsuhiro; Nishimura, Yasumasa; Saito, Kazunori; Matsukawa, Takayuki; Yoshihara, Tsutomu; Nakano, Takao.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Lewis Winner; Jack A.A. Raper; M. Winner; J. Raper; R.G. Swartz. Lewis Winner, 1985. p. 240-241.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kumanoya, M, Fujishima, K, Tsukamoto, K, Nishimura, Y, Saito, K, Matsukawa, T, Yoshihara, T & Nakano, T 1985, 90NS 1MB DRAM WITH MULTI-BIT TEST MODE. in L Winner, JAA Raper, M Winner, J Raper & RG Swartz (eds), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Lewis Winner, pp. 240-241.
Kumanoya M, Fujishima K, Tsukamoto K, Nishimura Y, Saito K, Matsukawa T et al. 90NS 1MB DRAM WITH MULTI-BIT TEST MODE. In Winner L, Raper JAA, Winner M, Raper J, Swartz RG, editors, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Lewis Winner. 1985. p. 240-241
Kumanoya, Masaki ; Fujishima, Kazuyasu ; Tsukamoto, Katsuhiro ; Nishimura, Yasumasa ; Saito, Kazunori ; Matsukawa, Takayuki ; Yoshihara, Tsutomu ; Nakano, Takao. / 90NS 1MB DRAM WITH MULTI-BIT TEST MODE. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / Lewis Winner ; Jack A.A. Raper ; M. Winner ; J. Raper ; R.G. Swartz. Lewis Winner, 1985. pp. 240-241
@inproceedings{02edb5acbc6a40d591c82935657fe403,
title = "90NS 1MB DRAM WITH MULTI-BIT TEST MODE.",
abstract = "Summary form only given. A single 5-V, 1-Mb NMOS DRAM is described that uses reliable memory cells with a reduced electric field and a shared sensing scheme for a reasonable cell signal. A testability concept, a page-nibble function, including continuous nibble mode, and an effective redundancy circuit are included. The memory cell uses a half Vcc cell plate that reduces the electric field across the oxide of the memory capacity to 50{\%} of that experienced with the conventional Vcc or Vss cell plate methods. A grounded epitaxial substrate is used to avoid the voltage bounce of the internally generated cell potential and minority carrier injection from the device inputs or peripheral circuits. The 35. 7- mu m**2 memory cell acts as a storage capacitance of 45 fF with 100-angstrom- thick oxide, while maintaining the electric field as low as 2 MV/cm.",
author = "Masaki Kumanoya and Kazuyasu Fujishima and Katsuhiro Tsukamoto and Yasumasa Nishimura and Kazunori Saito and Takayuki Matsukawa and Tsutomu Yoshihara and Takao Nakano",
year = "1985",
language = "English",
pages = "240--241",
editor = "Lewis Winner and Raper, {Jack A.A.} and M. Winner and J. Raper and R.G. Swartz",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Lewis Winner",

}

TY - GEN

T1 - 90NS 1MB DRAM WITH MULTI-BIT TEST MODE.

AU - Kumanoya, Masaki

AU - Fujishima, Kazuyasu

AU - Tsukamoto, Katsuhiro

AU - Nishimura, Yasumasa

AU - Saito, Kazunori

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

PY - 1985

Y1 - 1985

N2 - Summary form only given. A single 5-V, 1-Mb NMOS DRAM is described that uses reliable memory cells with a reduced electric field and a shared sensing scheme for a reasonable cell signal. A testability concept, a page-nibble function, including continuous nibble mode, and an effective redundancy circuit are included. The memory cell uses a half Vcc cell plate that reduces the electric field across the oxide of the memory capacity to 50% of that experienced with the conventional Vcc or Vss cell plate methods. A grounded epitaxial substrate is used to avoid the voltage bounce of the internally generated cell potential and minority carrier injection from the device inputs or peripheral circuits. The 35. 7- mu m**2 memory cell acts as a storage capacitance of 45 fF with 100-angstrom- thick oxide, while maintaining the electric field as low as 2 MV/cm.

AB - Summary form only given. A single 5-V, 1-Mb NMOS DRAM is described that uses reliable memory cells with a reduced electric field and a shared sensing scheme for a reasonable cell signal. A testability concept, a page-nibble function, including continuous nibble mode, and an effective redundancy circuit are included. The memory cell uses a half Vcc cell plate that reduces the electric field across the oxide of the memory capacity to 50% of that experienced with the conventional Vcc or Vss cell plate methods. A grounded epitaxial substrate is used to avoid the voltage bounce of the internally generated cell potential and minority carrier injection from the device inputs or peripheral circuits. The 35. 7- mu m**2 memory cell acts as a storage capacitance of 45 fF with 100-angstrom- thick oxide, while maintaining the electric field as low as 2 MV/cm.

UR - http://www.scopus.com/inward/record.url?scp=0022203558&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022203558&partnerID=8YFLogxK

M3 - Conference contribution

SP - 240

EP - 241

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Winner, Lewis

A2 - Raper, Jack A.A.

A2 - Winner, M.

A2 - Raper, J.

A2 - Swartz, R.G.

PB - Lewis Winner

ER -