A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement

Ruilin Zhang, Xingyu Wang, Kunyang Liu, Hirofumi Shinohara

Research output: Contribution to journalArticlepeer-review

Abstract

This article proposes a mismatch self-compensation latch-based true random number generator (TRNG) that harvests a metastable region's enhanced random noise. The proposed TRNG exhibits high randomness across a wide voltage (0.3-1.0 V) and temperature (-20 °C-100 °C) range by employing XOR of only four entropy sources (ESs). To achieve a full entropy output, an 8-bit von Neumann post-processing with waiting (VN8W) is used. The randomness of the TRNG's output is verified by NIST SP 800-22 and NIST SP 800-90B tests. The proposed TRNG, fabricated in 130-nm CMOS, achieves state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core (four ESs + XOR circuits) area of 661 μ m2 and a total area of 5561 μ m2, including VN8W. The robustness against power noise injection attacks is also demonstrated. An accelerating aging test revealed that the TRNG achieves a stable operation after 19 h of aging, which is equivalent to the 11-year life reliability. The mismatch-to-noise ratio analysis revealed that the XOR-OUT of TRNG core has more than 6 σ robustness against random mismatch variations.

Original languageEnglish
Pages (from-to)2498-2508
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume57
Issue number8
DOIs
Publication statusPublished - 2022 Aug 1

Keywords

  • Attack tolerant
  • cryptography
  • hardware security
  • latch
  • long-term reliability
  • low energy consumption
  • true random number generator (TRNG)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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