A 0.3mW 1.4mm2 motion estimation processor for mobile video application

Seiichiro Hiratsuka, Satoshi Goto, Takeshi Ikenaga

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-μm CMOS technology. 15K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm2 chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/sec ME processing.

Original languageEnglish
Pages103-106
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
Duration: 2006 Nov 132006 Nov 15

Conference

Conference2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
CountryChina
CityHangzhou
Period06/11/1306/11/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Hiratsuka, S., Goto, S., & Ikenaga, T. (2006). A 0.3mW 1.4mm2 motion estimation processor for mobile video application. 103-106. Paper presented at 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, Hangzhou, China. https://doi.org/10.1109/ASSCC.2006.357862