A 1 Gbin/s CABAC encoder for H.264/AVC

Wei Fei, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)

    Abstract

    In this paper, we propose a 1 Gbin/s context-based adaptive binary arithmetic coding (CABAC) encoder architecture for beyond-HDTV applications. CABAC is a crucial part in H.264/AVC main and high profiles that provides a great compression ratio at the expense of high computational complexity. And it is also considered as a very efficient coding method in the developing high-efficiency video coding (HEVC) standard. We try to accelerate the CABAC encoder to provide a high throughput to meet the requirement of beyond-HDTV video. Our design includes the binarization, context modeling and binary arithmetic encoding (BAE) parts and achieves a throughput of 4 bins per cycle. The synthesis result using SMIC 90nm shows that the logic gate count is 36.2K in all and the encoder engine can work at a maximum frequency of 279MHz. Thus the overall throughput can reach over 1 Gbin/s. In our design, the 460 contexts are assigned to 6 SRAMs to attain efficient context modeling. And the binarization part is also optimized to enhance the throughput with low hardware cost.

    Original languageEnglish
    Title of host publicationEuropean Signal Processing Conference
    Pages1524-1528
    Number of pages5
    Publication statusPublished - 2011
    Event19th European Signal Processing Conference, EUSIPCO 2011 - Barcelona, Spain
    Duration: 2011 Aug 292011 Sep 2

    Other

    Other19th European Signal Processing Conference, EUSIPCO 2011
    CountrySpain
    CityBarcelona
    Period11/8/2911/9/2

    Fingerprint

    Throughput
    High definition television
    Logic gates
    Static random access storage
    Bins
    Image coding
    Computational complexity
    Engines
    Hardware
    Costs

    ASJC Scopus subject areas

    • Signal Processing
    • Electrical and Electronic Engineering

    Cite this

    Fei, W., Zhou, D., & Goto, S. (2011). A 1 Gbin/s CABAC encoder for H.264/AVC. In European Signal Processing Conference (pp. 1524-1528)

    A 1 Gbin/s CABAC encoder for H.264/AVC. / Fei, Wei; Zhou, Dajiang; Goto, Satoshi.

    European Signal Processing Conference. 2011. p. 1524-1528.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Fei, W, Zhou, D & Goto, S 2011, A 1 Gbin/s CABAC encoder for H.264/AVC. in European Signal Processing Conference. pp. 1524-1528, 19th European Signal Processing Conference, EUSIPCO 2011, Barcelona, Spain, 11/8/29.
    Fei W, Zhou D, Goto S. A 1 Gbin/s CABAC encoder for H.264/AVC. In European Signal Processing Conference. 2011. p. 1524-1528
    Fei, Wei ; Zhou, Dajiang ; Goto, Satoshi. / A 1 Gbin/s CABAC encoder for H.264/AVC. European Signal Processing Conference. 2011. pp. 1524-1528
    @inproceedings{9b21ad34120d499692a7f4a768a975e7,
    title = "A 1 Gbin/s CABAC encoder for H.264/AVC",
    abstract = "In this paper, we propose a 1 Gbin/s context-based adaptive binary arithmetic coding (CABAC) encoder architecture for beyond-HDTV applications. CABAC is a crucial part in H.264/AVC main and high profiles that provides a great compression ratio at the expense of high computational complexity. And it is also considered as a very efficient coding method in the developing high-efficiency video coding (HEVC) standard. We try to accelerate the CABAC encoder to provide a high throughput to meet the requirement of beyond-HDTV video. Our design includes the binarization, context modeling and binary arithmetic encoding (BAE) parts and achieves a throughput of 4 bins per cycle. The synthesis result using SMIC 90nm shows that the logic gate count is 36.2K in all and the encoder engine can work at a maximum frequency of 279MHz. Thus the overall throughput can reach over 1 Gbin/s. In our design, the 460 contexts are assigned to 6 SRAMs to attain efficient context modeling. And the binarization part is also optimized to enhance the throughput with low hardware cost.",
    author = "Wei Fei and Dajiang Zhou and Satoshi Goto",
    year = "2011",
    language = "English",
    pages = "1524--1528",
    booktitle = "European Signal Processing Conference",

    }

    TY - GEN

    T1 - A 1 Gbin/s CABAC encoder for H.264/AVC

    AU - Fei, Wei

    AU - Zhou, Dajiang

    AU - Goto, Satoshi

    PY - 2011

    Y1 - 2011

    N2 - In this paper, we propose a 1 Gbin/s context-based adaptive binary arithmetic coding (CABAC) encoder architecture for beyond-HDTV applications. CABAC is a crucial part in H.264/AVC main and high profiles that provides a great compression ratio at the expense of high computational complexity. And it is also considered as a very efficient coding method in the developing high-efficiency video coding (HEVC) standard. We try to accelerate the CABAC encoder to provide a high throughput to meet the requirement of beyond-HDTV video. Our design includes the binarization, context modeling and binary arithmetic encoding (BAE) parts and achieves a throughput of 4 bins per cycle. The synthesis result using SMIC 90nm shows that the logic gate count is 36.2K in all and the encoder engine can work at a maximum frequency of 279MHz. Thus the overall throughput can reach over 1 Gbin/s. In our design, the 460 contexts are assigned to 6 SRAMs to attain efficient context modeling. And the binarization part is also optimized to enhance the throughput with low hardware cost.

    AB - In this paper, we propose a 1 Gbin/s context-based adaptive binary arithmetic coding (CABAC) encoder architecture for beyond-HDTV applications. CABAC is a crucial part in H.264/AVC main and high profiles that provides a great compression ratio at the expense of high computational complexity. And it is also considered as a very efficient coding method in the developing high-efficiency video coding (HEVC) standard. We try to accelerate the CABAC encoder to provide a high throughput to meet the requirement of beyond-HDTV video. Our design includes the binarization, context modeling and binary arithmetic encoding (BAE) parts and achieves a throughput of 4 bins per cycle. The synthesis result using SMIC 90nm shows that the logic gate count is 36.2K in all and the encoder engine can work at a maximum frequency of 279MHz. Thus the overall throughput can reach over 1 Gbin/s. In our design, the 460 contexts are assigned to 6 SRAMs to attain efficient context modeling. And the binarization part is also optimized to enhance the throughput with low hardware cost.

    UR - http://www.scopus.com/inward/record.url?scp=84863763663&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84863763663&partnerID=8YFLogxK

    M3 - Conference contribution

    AN - SCOPUS:84863763663

    SP - 1524

    EP - 1528

    BT - European Signal Processing Conference

    ER -