A 1-Mb STT-MRAM with zero-array standby power and 1.5-ns quick wake-up by 8-b fine-grained power gating

Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The power gating is one of the key technologies that reduce the operation power of STT-RAMs for enjoying their non-volatility. Especially, the number of memory cells whose supply voltages are simultaneously controlled in the power gating (grain size) is required to be as small as the bit-width in read and write for minimizing the operation power. For this ultra-fine-grained power gating scheme, we proposed a small power line (PL) driver that utilizes an NFET bootstrap circuit. It is found that the size of the macro using this PL driver is almost independent of the grain size with its write and read performance kept constant. Therefore, this PL driver combined with a small grain is shown to realize a nonvolatile embedded memory macro of fast read/write cycles, ultra-low operation power and zero array standby power with no leak path in the PL drivers.

Original languageEnglish
Title of host publication2013 5th IEEE International Memory Workshop, IMW 2013
Pages80-83
Number of pages4
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 5th IEEE International Memory Workshop, IMW 2013 - Monterey, CA, United States
Duration: 2013 May 262013 May 29

Other

Other2013 5th IEEE International Memory Workshop, IMW 2013
CountryUnited States
CityMonterey, CA
Period13/5/2613/5/29

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Keywords

  • bootstrap circuit
  • power gating
  • STT-RAM

ASJC Scopus subject areas

  • Software

Cite this

Ohsawa, T., Ikeda, S., Hanyu, T., Ohno, H., & Endoh, T. (2013). A 1-Mb STT-MRAM with zero-array standby power and 1.5-ns quick wake-up by 8-b fine-grained power gating. In 2013 5th IEEE International Memory Workshop, IMW 2013 (pp. 80-83). [6582103] https://doi.org/10.1109/IMW.2013.6582103