A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; Kazuo Kyuma

doi:10.1109/4.641691

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced "FD-PD mode switching" transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current.

Original language	English
Pages (from-to)	1712-1718
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	32
Issue number	11
DOIs	https://doi.org/10.1109/4.641691
Publication status	Published - 1997 Nov
Externally published	Yes

Keywords

CMOS integrated circuits
Circuit simulation
DRAM chips
Integrated circuit design
Silicon-on-insulator technology

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/4.641691

Fingerprint Dive into the research topics of 'A 1-V 46-ns 16-Mb SOI-DRAM with body control technique'. Together they form a unique fingerprint.

Cite this

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. / Shimomura, Ken'ichi; Shimano, Hiroki; Sakashita, Narumi; Okuda, Fumihiro; Oashi, Toshiyuki; Yamaguchi, Yasuo; Eimori, Takahisa; Inuishi, Masahide; Arimoto, Kazutami; Maegawa, Shigeto; Inoue, Yasuo; Komori, Shinji; Kyuma, Kazuo.

In: IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, 11.1997, p. 1712-1718.

Research output: Contribution to journal › Article › peer-review

Shimomura, Ken'ichi ; Shimano, Hiroki ; Sakashita, Narumi ; Okuda, Fumihiro ; Oashi, Toshiyuki ; Yamaguchi, Yasuo ; Eimori, Takahisa ; Inuishi, Masahide ; Arimoto, Kazutami ; Maegawa, Shigeto ; Inoue, Yasuo ; Komori, Shinji ; Kyuma, Kazuo. / A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. In: IEEE Journal of Solid-State Circuits. 1997 ; Vol. 32, No. 11. pp. 1712-1718.

@article{41a9d204d72c4125b5845c856b87e7ef,

title = "A 1-V 46-ns 16-Mb SOI-DRAM with body control technique",

abstract = "A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced {"}FD-PD mode switching{"} transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current.",

keywords = "CMOS integrated circuits, Circuit simulation, DRAM chips, Integrated circuit design, Silicon-on-insulator technology",

author = "Ken'ichi Shimomura and Hiroki Shimano and Narumi Sakashita and Fumihiro Okuda and Toshiyuki Oashi and Yasuo Yamaguchi and Takahisa Eimori and Masahide Inuishi and Kazutami Arimoto and Shigeto Maegawa and Yasuo Inoue and Shinji Komori and Kazuo Kyuma",

year = "1997",

month = nov,

doi = "10.1109/4.641691",

language = "English",

volume = "32",

pages = "1712--1718",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

AU - Shimomura, Ken'ichi

AU - Shimano, Hiroki

AU - Sakashita, Narumi

AU - Okuda, Fumihiro

AU - Oashi, Toshiyuki

AU - Yamaguchi, Yasuo

AU - Eimori, Takahisa

AU - Inuishi, Masahide

AU - Arimoto, Kazutami

AU - Maegawa, Shigeto

AU - Inoue, Yasuo

AU - Komori, Shinji

AU - Kyuma, Kazuo

PY - 1997/11

Y1 - 1997/11

N2 - A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced "FD-PD mode switching" transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current.

AB - A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced "FD-PD mode switching" transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current.

KW - CMOS integrated circuits

KW - Circuit simulation

KW - DRAM chips

KW - Integrated circuit design

KW - Silicon-on-insulator technology

UR - http://www.scopus.com/inward/record.url?scp=0031270360&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031270360&partnerID=8YFLogxK

U2 - 10.1109/4.641691

DO - 10.1109/4.641691

M3 - Article

AN - SCOPUS:0031270360

VL - 32

SP - 1712

EP - 1718

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 11

ER -