A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced "FD-PD mode switching" transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current.

Original languageEnglish
Pages (from-to)1712-1718
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume32
Issue number11
DOIs
Publication statusPublished - 1997 Nov

Keywords

  • CMOS integrated circuits
  • Circuit simulation
  • DRAM chips
  • Integrated circuit design
  • Silicon-on-insulator technology

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Shimomura, K., Shimano, H., Sakashita, N., Okuda, F., Oashi, T., Yamaguchi, Y., Eimori, T., Inuishi, M., Arimoto, K., Maegawa, S., Inoue, Y., Komori, S., & Kyuma, K. (1997). A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE Journal of Solid-State Circuits, 32(11), 1712-1718. https://doi.org/10.1109/4.641691