A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

Katsumi Dosaka; Yasuhiro Konishi; Kouji Hayano; Katsumitsu Himukashi; Akira Yamazaki; Hisashi Iwamoto; Masaki Kumanoya; Hisanori Hamano; Tsutomu Yoshihara

doi:10.1109/4.165333

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

Katsumi Dosaka^*, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm² is only a 7% increase over the conventional 4-MB DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.

Original language	English
Pages (from-to)	1534-1539
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	27
Issue number	11
DOIs	https://doi.org/10.1109/4.165333
Publication status	Published - 1992 Nov
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.165333

Cite this

@article{f5f26962ccd84561867c807bb1872490,

title = "A 100-MHz 4-Mb cache DRAM with fast copy-back scheme",

abstract = "A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-MB DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.",

author = "Katsumi Dosaka and Yasuhiro Konishi and Kouji Hayano and Katsumitsu Himukashi and Akira Yamazaki and Hisashi Iwamoto and Masaki Kumanoya and Hisanori Hamano and Tsutomu Yoshihara",

year = "1992",

month = nov,

doi = "10.1109/4.165333",

language = "English",

volume = "27",

pages = "1534--1539",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

AU - Dosaka, Katsumi

AU - Konishi, Yasuhiro

AU - Hayano, Kouji

AU - Himukashi, Katsumitsu

AU - Yamazaki, Akira

AU - Iwamoto, Hisashi

AU - Kumanoya, Masaki

AU - Hamano, Hisanori

AU - Yoshihara, Tsutomu

PY - 1992/11

Y1 - 1992/11

N2 - A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-MB DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.

AB - A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-MB DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.

UR - http://www.scopus.com/inward/record.url?scp=0026954380&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026954380&partnerID=8YFLogxK

U2 - 10.1109/4.165333

DO - 10.1109/4.165333

M3 - Article

AN - SCOPUS:0026954380

SN - 0018-9200

VL - 27

SP - 1534

EP - 1539

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 11

ER -

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

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