A 100MHz dual port (DP) MRAM with swing-less bit-line sensing (SLBS) operation for high-end microcomputer systems

Hu Li, Leona Okamura, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In this paper, we propose two kinds of implementations of the dual port MRAM, one of which is for the read/write concurrent operation while another is for the additional simultaneous read operation. Compared with dual port SRAM, the dual port MRAM accompanied with smaller memory cell size will make high performance systems realized in the mobile/robotics field. A swing-less bit-line sensing (SLBS) technique and the static bitline level in the read mode, help to realize the high performance under the condition of Vcc=1.0V and the operation frequency of 100MHz.

    Original languageEnglish
    Title of host publication2006 International Symposium on Communications and Information Technologies, ISCIT
    Pages63-66
    Number of pages4
    DOIs
    Publication statusPublished - 2006
    Event2006 International Symposium on Communications and Information Technologies, ISCIT - Bangkok
    Duration: 2006 Oct 182006 Oct 20

    Other

    Other2006 International Symposium on Communications and Information Technologies, ISCIT
    CityBangkok
    Period06/10/1806/10/20

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Li, H., Okamura, L., Yoshihara, T., Ooishi, T., & Kihara, Y. (2006). A 100MHz dual port (DP) MRAM with swing-less bit-line sensing (SLBS) operation for high-end microcomputer systems. In 2006 International Symposium on Communications and Information Technologies, ISCIT (pp. 63-66). [4141514] https://doi.org/10.1109/ISCIT.2006.339888