A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

Dajiang Zhou, Zongyuan You, Jiayi Zhu, Ji Kong, Yu Hong, Xianmin Chen, Xuewen He, Chen Xu, Hang Zhang, Jinjia Zhou, Ning Deng, Peilin Liu, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages262-263
Number of pages2
Publication statusPublished - 2009
Externally publishedYes
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09/6/1609/6/18

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Zhou, D., You, Z., Zhu, J., Kong, J., Hong, Y., Chen, X., He, X., Xu, C., Zhang, H., Zhou, J., Deng, N., Liu, P., & Goto, S. (2009). A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 262-263). [5205354]