A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology

Naoko Ono, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10-8. The transmitter has an output power of -0.05 dBm.

Original languageEnglish
Title of host publication2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
Pages439-441
Number of pages3
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, Taiwan, Province of China
Duration: 2012 Dec 42012 Dec 7

Other

Other2012 Asia-Pacific Microwave Conference, APMC 2012
CountryTaiwan, Province of China
CityKaohsiung
Period12/12/412/12/7

    Fingerprint

Keywords

  • ASK
  • data rate
  • Millimeter-wave
  • receiver
  • transmitter
  • wireless

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ono, N., Motoyoshi, M., Takano, K., Katayama, K., Fujimoto, R., & Fujishima, M. (2012). A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology. In 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings (pp. 439-441). [6421624] https://doi.org/10.1109/APMC.2012.6421624