A 12-bit 3.7-msample/s pipelined A/D converter based on the novel capacitor mismatch calibration technique

Shuaiqi Wang, Fule Li, Yasuaki Inoue

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 μm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

    Original languageEnglish
    Pages (from-to)2465-2474
    Number of pages10
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE91-A
    Issue number9
    DOIs
    Publication statusPublished - 2008 Sep

    Fingerprint

    Capacitor
    Converter
    Calibration
    Capacitors
    Dissipation
    Energy dissipation
    Charge
    Analog Circuits
    Analog circuits
    Redistribution
    Linearity
    Switch
    Transistors
    Switches
    Verify
    Networks (circuits)
    Simulation

    Keywords

    • A/D conversion
    • Capacitor mismatch calibration
    • Low power dissipation
    • Pipelined

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    Cite this

    A 12-bit 3.7-msample/s pipelined A/D converter based on the novel capacitor mismatch calibration technique. / Wang, Shuaiqi; Li, Fule; Inoue, Yasuaki.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No. 9, 09.2008, p. 2465-2474.

    Research output: Contribution to journalArticle

    @article{40eb936b65494f2c991ab60b6a6ca878,
    title = "A 12-bit 3.7-msample/s pipelined A/D converter based on the novel capacitor mismatch calibration technique",
    abstract = "This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 μm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.",
    keywords = "A/D conversion, Capacitor mismatch calibration, Low power dissipation, Pipelined",
    author = "Shuaiqi Wang and Fule Li and Yasuaki Inoue",
    year = "2008",
    month = "9",
    doi = "10.1093/ietfec/e91-a.9.2465",
    language = "English",
    volume = "E91-A",
    pages = "2465--2474",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "9",

    }

    TY - JOUR

    T1 - A 12-bit 3.7-msample/s pipelined A/D converter based on the novel capacitor mismatch calibration technique

    AU - Wang, Shuaiqi

    AU - Li, Fule

    AU - Inoue, Yasuaki

    PY - 2008/9

    Y1 - 2008/9

    N2 - This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 μm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

    AB - This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 μm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

    KW - A/D conversion

    KW - Capacitor mismatch calibration

    KW - Low power dissipation

    KW - Pipelined

    UR - http://www.scopus.com/inward/record.url?scp=77953461955&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=77953461955&partnerID=8YFLogxK

    U2 - 10.1093/ietfec/e91-a.9.2465

    DO - 10.1093/ietfec/e91-a.9.2465

    M3 - Article

    AN - SCOPUS:77953461955

    VL - E91-A

    SP - 2465

    EP - 2474

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 9

    ER -