A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Tohru Furuyama; Yousei Nagahama

doi:10.1109/4.75042

A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Tohru Furuyama, Yousei Nagahama

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

Original language	English
Pages (from-to)	479-483
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	26
Issue number	4
DOIs	https://doi.org/10.1109/4.75042
Publication status	Published - 1991 Apr
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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abstract = "A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.",

author = "Natsuki Kushiyama and Yohji Watanabe and Takashi Ohsawa and Kazuyoshi Muraoka and Tohru Furuyama and Yousei Nagahama",

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AU - Kushiyama, Natsuki

AU - Watanabe, Yohji

AU - Ohsawa, Takashi

AU - Muraoka, Kazuyoshi

AU - Furuyama, Tohru

AU - Nagahama, Yousei

PY - 1991/4

Y1 - 1991/4

N2 - A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

AB - A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

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A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

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