A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Tohru Furuyama; Yousei Nagahama

doi:10.1109/4.75042

A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Tohru Furuyama, Yousei Nagahama

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

Original language	English
Pages (from-to)	479-483
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	26
Issue number	4
DOIs	https://doi.org/10.1109/4.75042
Publication status	Published - 1991 Apr
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/4.75042

Fingerprint Dive into the research topics of 'A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation'. Together they form a unique fingerprint.

Cite this

@article{8f8e5b35caf147a3a1d13e707982ef94,

title = "A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation",

abstract = "A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.",

author = "Natsuki Kushiyama and Yohji Watanabe and Takashi Ohsawa and Kazuyoshi Muraoka and Tohru Furuyama and Yousei Nagahama",

year = "1991",

month = apr,

doi = "10.1109/4.75042",

language = "English",

volume = "26",

pages = "479--483",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

AU - Kushiyama, Natsuki

AU - Watanabe, Yohji

AU - Ohsawa, Takashi

AU - Muraoka, Kazuyoshi

AU - Furuyama, Tohru

AU - Nagahama, Yousei

PY - 1991/4

Y1 - 1991/4

N2 - A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

AB - A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

UR - http://www.scopus.com/inward/record.url?scp=0026138571&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026138571&partnerID=8YFLogxK

U2 - 10.1109/4.75042

DO - 10.1109/4.75042

M3 - Article

AN - SCOPUS:0026138571

VL - 26

SP - 479

EP - 483

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -

A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Cite this