A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Tohru Furuyama; Yousei Nagahama

doi:10.1109/4.75042

A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Tohru Furuyama, Yousei Nagahama

Research output: Contribution to journal › Article

2 Citations (Scopus)

Abstract

A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

Original language	English
Pages (from-to)	479-483
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	26
Issue number	4
DOIs	https://doi.org/10.1109/4.75042
Publication status	Published - 1991
Externally published	Yes

Fingerprint

Dynamic random access storage

Pipelines

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Kushiyama, N., Watanabe, Y., Ohsawa, T., Muraoka, K., Furuyama, T., & Nagahama, Y. (1991). A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation. IEEE Journal of Solid-State Circuits, 26(4), 479-483. https://doi.org/10.1109/4.75042

A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation. / Kushiyama, Natsuki; Watanabe, Yohji; Ohsawa, Takashi; Muraoka, Kazuyoshi; Furuyama, Tohru; Nagahama, Yousei.

In: IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, 1991, p. 479-483.

Research output: Contribution to journal › Article

Kushiyama, N, Watanabe, Y, Ohsawa, T, Muraoka, K, Furuyama, T & Nagahama, Y 1991, 'A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation', IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 479-483. https://doi.org/10.1109/4.75042

Kushiyama N, Watanabe Y, Ohsawa T, Muraoka K, Furuyama T, Nagahama Y. A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation. IEEE Journal of Solid-State Circuits. 1991;26(4):479-483. https://doi.org/10.1109/4.75042

Kushiyama, Natsuki ; Watanabe, Yohji ; Ohsawa, Takashi ; Muraoka, Kazuyoshi ; Furuyama, Tohru ; Nagahama, Yousei. / A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation. In: IEEE Journal of Solid-State Circuits. 1991 ; Vol. 26, No. 4. pp. 479-483.

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Access to Document

10.1109/4.75042