A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

Hajime Kubosawa, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai

    Research output: Contribution to journalArticle

    3 Citations (Scopus)

    Abstract

    We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including a) MPEG2 (MP@Ml.) decoding and graphic processing capabilities for three-dimensional images, b) programming flexibility. and c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84 × 10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.

    Original languageEnglish
    Pages (from-to)1640-1646
    Number of pages7
    JournalIEEE Journal of Solid-State Circuits
    Volume33
    Issue number11
    DOIs
    Publication statusPublished - 1998 Nov

    Fingerprint

    Microprocessor chips
    Electric power utilization
    Embedded systems
    Decoding
    Reduced instruction set computing
    Processing
    Image processing
    Controllers
    Networks (circuits)
    Metals
    Costs

    Keywords

    • Embedded microprocessors
    • MPEG2
    • Multimedia
    • Programming flexibility
    • Single instruction multiple data stream
    • Superscalar

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Kubosawa, H., Takahashi, H., Ando, S., Asada, Y., Asato, A., Suga, A., ... Mitarai, S. (1998). A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. IEEE Journal of Solid-State Circuits, 33(11), 1640-1646. https://doi.org/10.1109/4.726550

    A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. / Kubosawa, Hajime; Takahashi, Hiromasa; Ando, Satoshi; Asada, Yoshimi; Asato, Akira; Suga, Atsuhiro; Kimura, Michihide; Higaki, Naoshi; Miyake, Hideo; Sato, Tomio; Anbutsu, Hideaki; Tsuda, Toshitaka; Yoshimura, Tetsuo; Amano, Isao; Kai, Mutsuaki; Mitarai, Shin.

    In: IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, 11.1998, p. 1640-1646.

    Research output: Contribution to journalArticle

    Kubosawa, H, Takahashi, H, Ando, S, Asada, Y, Asato, A, Suga, A, Kimura, M, Higaki, N, Miyake, H, Sato, T, Anbutsu, H, Tsuda, T, Yoshimura, T, Amano, I, Kai, M & Mitarai, S 1998, 'A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications', IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp. 1640-1646. https://doi.org/10.1109/4.726550
    Kubosawa, Hajime ; Takahashi, Hiromasa ; Ando, Satoshi ; Asada, Yoshimi ; Asato, Akira ; Suga, Atsuhiro ; Kimura, Michihide ; Higaki, Naoshi ; Miyake, Hideo ; Sato, Tomio ; Anbutsu, Hideaki ; Tsuda, Toshitaka ; Yoshimura, Tetsuo ; Amano, Isao ; Kai, Mutsuaki ; Mitarai, Shin. / A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. In: IEEE Journal of Solid-State Circuits. 1998 ; Vol. 33, No. 11. pp. 1640-1646.
    @article{b193cf91973548f18a094b5a20ba6443,
    title = "A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications",
    abstract = "We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including a) MPEG2 (MP@Ml.) decoding and graphic processing capabilities for three-dimensional images, b) programming flexibility. and c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84 × 10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.",
    keywords = "Embedded microprocessors, MPEG2, Multimedia, Programming flexibility, Single instruction multiple data stream, Superscalar",
    author = "Hajime Kubosawa and Hiromasa Takahashi and Satoshi Ando and Yoshimi Asada and Akira Asato and Atsuhiro Suga and Michihide Kimura and Naoshi Higaki and Hideo Miyake and Tomio Sato and Hideaki Anbutsu and Toshitaka Tsuda and Tetsuo Yoshimura and Isao Amano and Mutsuaki Kai and Shin Mitarai",
    year = "1998",
    month = "11",
    doi = "10.1109/4.726550",
    language = "English",
    volume = "33",
    pages = "1640--1646",
    journal = "IEEE Journal of Solid-State Circuits",
    issn = "0018-9200",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",
    number = "11",

    }

    TY - JOUR

    T1 - A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

    AU - Kubosawa, Hajime

    AU - Takahashi, Hiromasa

    AU - Ando, Satoshi

    AU - Asada, Yoshimi

    AU - Asato, Akira

    AU - Suga, Atsuhiro

    AU - Kimura, Michihide

    AU - Higaki, Naoshi

    AU - Miyake, Hideo

    AU - Sato, Tomio

    AU - Anbutsu, Hideaki

    AU - Tsuda, Toshitaka

    AU - Yoshimura, Tetsuo

    AU - Amano, Isao

    AU - Kai, Mutsuaki

    AU - Mitarai, Shin

    PY - 1998/11

    Y1 - 1998/11

    N2 - We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including a) MPEG2 (MP@Ml.) decoding and graphic processing capabilities for three-dimensional images, b) programming flexibility. and c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84 × 10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.

    AB - We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including a) MPEG2 (MP@Ml.) decoding and graphic processing capabilities for three-dimensional images, b) programming flexibility. and c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84 × 10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.

    KW - Embedded microprocessors

    KW - MPEG2

    KW - Multimedia

    KW - Programming flexibility

    KW - Single instruction multiple data stream

    KW - Superscalar

    UR - http://www.scopus.com/inward/record.url?scp=0032206116&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0032206116&partnerID=8YFLogxK

    U2 - 10.1109/4.726550

    DO - 10.1109/4.726550

    M3 - Article

    VL - 33

    SP - 1640

    EP - 1646

    JO - IEEE Journal of Solid-State Circuits

    JF - IEEE Journal of Solid-State Circuits

    SN - 0018-9200

    IS - 11

    ER -