A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput

Hiroshi Nakamura, Kenichi Imamiya, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian Chen

Research output: Contribution to journal › Conference article

1 Citation (Scopus)

Abstract

A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

Original languageEnglish
Pages (from-to)82-83+411
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Issue numberSUPPL.
Publication statusPublished - 2002 Jan 1
Externally publishedYes
Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 3 → 2002 Feb 7

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Flash memory
Throughput

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Nakamura, H., Imamiya, K., Himeno, T., Yamamura, T., Ikehashi, T., Takeuchi, K., ... Chen, J. (2002). A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, (SUPPL.), 82-83+411.

A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput. / Nakamura, Hiroshi; Imamiya, Kenichi; Himeno, Toshihiko; Yamamura, Toshio; Ikehashi, Tamio; Takeuchi, Ken; Kanda, Kazushige; Hosono, Koji; Futatsuyama, Takuya; Kawai, Koichi; Shirota, Riichiro; Arai, Norihisa; Arai, Fumitaka; Hatakeyama, Kazuo; Hazama, Hiroaki; Saito, Masanobu; Meguro, Hisataka; Conley, Kevin; Quader, Khandker; Chen, Jian.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, No. SUPPL., 01.01.2002, p. 82-83+411.

Research output: Contribution to journal › Conference article

Nakamura, H, Imamiya, K, Himeno, T, Yamamura, T, Ikehashi, T, Takeuchi, K, Kanda, K, Hosono, K, Futatsuyama, T, Kawai, K, Shirota, R, Arai, N, Arai, F, Hatakeyama, K, Hazama, H, Saito, M, Meguro, H, Conley, K, Quader, K & Chen, J 2002, 'A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput', Digest of Technical Papers - IEEE International Solid-State Circuits Conference, no. SUPPL., pp. 82-83+411.
Nakamura H, Imamiya K, Himeno T, Yamamura T, Ikehashi T, Takeuchi K et al. A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2002 Jan 1;(SUPPL.):82-83+411.
Nakamura, Hiroshi ; Imamiya, Kenichi ; Himeno, Toshihiko ; Yamamura, Toshio ; Ikehashi, Tamio ; Takeuchi, Ken ; Kanda, Kazushige ; Hosono, Koji ; Futatsuyama, Takuya ; Kawai, Koichi ; Shirota, Riichiro ; Arai, Norihisa ; Arai, Fumitaka ; Hatakeyama, Kazuo ; Hazama, Hiroaki ; Saito, Masanobu ; Meguro, Hisataka ; Conley, Kevin ; Quader, Khandker ; Chen, Jian. / A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2002 ; No. SUPPL. pp. 82-83+411.
@article{4ddcad6cbe9a4e13a5cfb5a8e38af820,
title = "A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput",
abstract = "A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.",
author = "Hiroshi Nakamura and Kenichi Imamiya and Toshihiko Himeno and Toshio Yamamura and Tamio Ikehashi and Ken Takeuchi and Kazushige Kanda and Koji Hosono and Takuya Futatsuyama and Koichi Kawai and Riichiro Shirota and Norihisa Arai and Fumitaka Arai and Kazuo Hatakeyama and Hiroaki Hazama and Masanobu Saito and Hisataka Meguro and Kevin Conley and Khandker Quader and Jian Chen",
year = "2002",
month = "1",
day = "1",
language = "English",
pages = "82--83+411",
journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
issn = "0193-6530",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "SUPPL.",

}

TY - JOUR

T1 - A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput

AU - Nakamura, Hiroshi

AU - Imamiya, Kenichi

AU - Himeno, Toshihiko

AU - Yamamura, Toshio

AU - Ikehashi, Tamio

AU - Takeuchi, Ken

AU - Kanda, Kazushige

AU - Hosono, Koji

AU - Futatsuyama, Takuya

AU - Kawai, Koichi

AU - Shirota, Riichiro

AU - Arai, Norihisa

AU - Arai, Fumitaka

AU - Hatakeyama, Kazuo

AU - Hazama, Hiroaki

AU - Saito, Masanobu

AU - Meguro, Hisataka

AU - Conley, Kevin

AU - Quader, Khandker

AU - Chen, Jian

PY - 2002/1/1

Y1 - 2002/1/1

N2 - A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

AB - A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

UR - http://www.scopus.com/inward/record.url?scp=0036224005&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036224005&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0036224005

SP - 82-83+411

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

IS - SUPPL.

ER -

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