A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput

Hiroshi Nakamura, Kenichi Imamiya, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian Chen

Research output: Contribution to journalConference article

2 Citations (Scopus)

Abstract

A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

Original languageEnglish
Pages (from-to)82-83+411
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Issue numberSUPPL.
Publication statusPublished - 2002 Jan 1
Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 32002 Feb 7

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Nakamura, H., Imamiya, K., Himeno, T., Yamamura, T., Ikehashi, T., Takeuchi, K., Kanda, K., Hosono, K., Futatsuyama, T., Kawai, K., Shirota, R., Arai, N., Arai, F., Hatakeyama, K., Hazama, H., Saito, M., Meguro, H., Conley, K., Quader, K., & Chen, J. (2002). A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, (SUPPL.), 82-83+411.