Abstract
A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.
Original language | English |
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Pages (from-to) | 82-83+411 |
Journal | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
Issue number | SUPPL. |
Publication status | Published - 2002 Jan 1 |
Externally published | Yes |
Event | 2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States Duration: 2002 Feb 3 → 2002 Feb 7 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering