A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell

Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Tomoaki Shino, Hiroomi Nakajima, Yoshihiro Minami, Naoki Kusunoki, Atsushi Sakamoto, Jun Nishimura, Takeshi Hamamoto, Shuso Fujii

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A 128Mbit FBRAM using the floating body cell(FBC) the size of 0.17μm2(6.24F2 with F-0.165μm) was successfully fabricated and a high bit yield(∼99.999%) was obtained.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages180-181
Number of pages2
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period06/6/1506/6/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Ohsawa, T., Higashi, T., Fujita, K., Hatsuda, K., Ikumi, N., Shino, T., Nakajima, H., Minami, Y., Kusunoki, N., Sakamoto, A., Nishimura, J., Hamamoto, T., & Fujii, S. (2006). A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell. In 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 180-181). [1705369] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).