A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki, S. Miyano, T. Sakurai, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages60-61
Number of pages2
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
Duration: 2012 Jun 132012 Jun 15

Other

Other2012 Symposium on VLSI Circuits, VLSIC 2012
CountryUnited States
CityHonolulu, HI
Period12/6/1312/6/15

Fingerprint

Static random access storage
Networks (circuits)
Electric power utilization
Electric potential

Keywords

  • 6T
  • charge-share
  • SRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Miyano, S., Sakurai, T., & Shinohara, H. (2012). A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 60-61). [6243789] https://doi.org/10.1109/VLSIC.2012.6243789

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. / Moriwaki, S.; Yamamoto, Y.; Kawasumi, A.; Suzuki, T.; Miyano, S.; Sakurai, T.; Shinohara, Hirofumi.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2012. p. 60-61 6243789.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Moriwaki, S, Yamamoto, Y, Kawasumi, A, Suzuki, T, Miyano, S, Sakurai, T & Shinohara, H 2012, A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 6243789, pp. 60-61, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 12/6/13. https://doi.org/10.1109/VLSIC.2012.6243789
Moriwaki S, Yamamoto Y, Kawasumi A, Suzuki T, Miyano S, Sakurai T et al. A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2012. p. 60-61. 6243789 https://doi.org/10.1109/VLSIC.2012.6243789
Moriwaki, S. ; Yamamoto, Y. ; Kawasumi, A. ; Suzuki, T. ; Miyano, S. ; Sakurai, T. ; Shinohara, Hirofumi. / A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2012. pp. 60-61
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