Abstract
A high efficiency linear power amplifier (PA) IC is presented for 14 GHz-band wireless communication systems. A novel adaptive bias circuit with four-stacked MOSFET structure is proposed to enhance both the linearity and efficiency of the PA IC over the wide input power range. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS. In linear mode, the PA IC has exhibited an output P1dB of 20.1 dBm at 14 GHz and a supply voltage of 4.0 V. The measured PAE at P1dB is as high as 40.1%. Moreover, the peak PAE of 41.6% is achieved in efficient mode.
| Original language | English |
|---|---|
| Title of host publication | EuMIC 2018 - 2018 13th European Microwave Integrated Circuits Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 182-185 |
| Number of pages | 4 |
| ISBN (Electronic) | 9782874870521 |
| DOIs | |
| Publication status | Published - 2018 Nov 16 |
| Event | 13th European Microwave Integrated Circuits Conference, EuMIC 2018 - Madrid, Spain Duration: 2018 Sep 24 → 2018 Sep 25 |
Other
| Other | 13th European Microwave Integrated Circuits Conference, EuMIC 2018 |
|---|---|
| Country | Spain |
| City | Madrid |
| Period | 18/9/24 → 18/9/25 |
Keywords
- adaptive bias circuit
- high efficiency
- high linearity
- SOI CMOS
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
- Instrumentation
Fingerprint Dive into the research topics of 'A 14-GHz-Band Highly Linear Stacked FET Power Amplifier IC with 20.1 dBm P1dB and 40.1% PAE in 56-nm SOI CMOS'. Together they form a unique fingerprint.
Cite this
Chen, C., Sugiura, T., & Yoshimasu, T. (2018). A 14-GHz-Band Highly Linear Stacked FET Power Amplifier IC with 20.1 dBm P1dB and 40.1% PAE in 56-nm SOI CMOS. In EuMIC 2018 - 2018 13th European Microwave Integrated Circuits Conference (pp. 182-185). [8539942] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/EuMIC.2018.8539942