A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

Shuaiqi Wang, Fule Li, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

    Original languageEnglish
    Title of host publication2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
    Pages2176-2180
    Number of pages5
    Volume4
    DOIs
    Publication statusPublished - 2006
    Event2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin
    Duration: 2006 Jun 252006 Jun 28

    Other

    Other2006 International Conference on Communications, Circuits and Systems, ICCCAS
    CityGuilin
    Period06/6/2506/6/28

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Wang, S., Li, F., & Inoue, Y. (2006). A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle. In 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings (Vol. 4, pp. 2176-2180). [4064355] https://doi.org/10.1109/ICCCAS.2006.285108