A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder

Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23%. DRAM bandwidth requirement is reduced by 68%. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed ME processor well accommodates the large motion of ultra-high-resolution video.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publication statusPublished - 2013
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 2013 Jun 122013 Jun 14

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period13/6/1213/6/14

Fingerprint

Motion estimation
Dynamic random access storage
Energy efficiency
Energy dissipation
Throughput
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Zhou, J., Zhou, D., He, G., & Goto, S. (2013). A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers [6578697]

A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder. / Zhou, Jinjia; Zhou, Dajiang; He, Gang; Goto, Satoshi.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578697.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhou, J, Zhou, D, He, G & Goto, S 2013, A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 6578697, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.
Zhou J, Zhou D, He G, Goto S. A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578697
Zhou, Jinjia ; Zhou, Dajiang ; He, Gang ; Goto, Satoshi. / A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013.
@inproceedings{a4314737a4b04a8a87ec517cea8288ae,
title = "A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder",
abstract = "A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23{\%}. DRAM bandwidth requirement is reduced by 68{\%}. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed ME processor well accommodates the large motion of ultra-high-resolution video.",
author = "Jinjia Zhou and Dajiang Zhou and Gang He and Satoshi Goto",
year = "2013",
language = "English",
isbn = "9784863483484",
booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

}

TY - GEN

T1 - A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder

AU - Zhou, Jinjia

AU - Zhou, Dajiang

AU - He, Gang

AU - Goto, Satoshi

PY - 2013

Y1 - 2013

N2 - A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23%. DRAM bandwidth requirement is reduced by 68%. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed ME processor well accommodates the large motion of ultra-high-resolution video.

AB - A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23%. DRAM bandwidth requirement is reduced by 68%. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed ME processor well accommodates the large motion of ultra-high-resolution video.

UR - http://www.scopus.com/inward/record.url?scp=84883827842&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883827842&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84883827842

SN - 9784863483484

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

ER -