A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

Takashi Ohsawa, S. Miura, K. Kinoshita, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

A 1Mb STT-RAM with a 6T2MTJ cell is designed and fabricated using 90nm CMOS/MTJ process that can operate in 1.5nsec/2.1nsec random read/write cycle by adopting a background write scheme. It works around the problem of high error rate of MTJ switching in a short period of time at moderate drive current. The RAM is fast enough to be applicable to embedded memories such as L3 cache.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Publication statusPublished - 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 2013 Jun 122013 Jun 14

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period13/6/1213/6/14

Fingerprint

Random access storage
Data storage equipment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Ohsawa, T., Miura, S., Kinoshita, K., Honjo, H., Ikeda, S., Hanyu, T., ... Endoh, T. (2013). A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers [6578738]

A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories. / Ohsawa, Takashi; Miura, S.; Kinoshita, K.; Honjo, H.; Ikeda, S.; Hanyu, T.; Ohno, H.; Endoh, T.

2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. 6578738.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ohsawa, T, Miura, S, Kinoshita, K, Honjo, H, Ikeda, S, Hanyu, T, Ohno, H & Endoh, T 2013, A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories. in 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578738, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.
Ohsawa T, Miura S, Kinoshita K, Honjo H, Ikeda S, Hanyu T et al. A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. 6578738
Ohsawa, Takashi ; Miura, S. ; Kinoshita, K. ; Honjo, H. ; Ikeda, S. ; Hanyu, T. ; Ohno, H. ; Endoh, T. / A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories. 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013.
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