A 16-65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications

Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a motion compensation architecture for Quad-HD H.264/AVC video decoder. For meeting the high throughput requirement, reducing power consumption and solving the memory latency problems, three optimization schemes are applied in this work. Firstly, a quarter-pel interpolator based on Horizontal-Vertical Expansion and Luma-Chroma Parallelism (HVE-LCP) is proposed to efficiently increase the throughput by at least 4 times from the previous designs. Secondly, a novel cache memory organization (4S×4) is adopted to improve the on-chip memory utilization, contributing to memory area and power saving. Finally, a Split Task Queue (STQ) architecture enhances the memory system latency tolerance, which reduces overall processing time. This design costs a logic gate count and on-chip memory of 108.8k and 3.1kB, respectively. The proposed architecture supports real-time processing of 3840×2160@60fps at 166MHz.

Original languageEnglish
Title of host publicationEuropean Signal Processing Conference
Pages729-733
Number of pages5
Publication statusPublished - 2011
Event19th European Signal Processing Conference, EUSIPCO 2011 - Barcelona, Spain
Duration: 2011 Aug 292011 Sep 2

Other

Other19th European Signal Processing Conference, EUSIPCO 2011
CountrySpain
CityBarcelona
Period11/8/2911/9/2

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

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  • Cite this

    Zhou, J., Zhou, D., He, G., & Goto, S. (2011). A 16-65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications. In European Signal Processing Conference (pp. 729-733)